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From: Laurent Vivier <laurent@vivier.eu>
To: qemu-devel@nongnu.org
Cc: schwab@linux-m68k.org, agraf@suse.de,
	Richard Henderson <rth@twiddle.net>,
	gerg@uclinux.org, Laurent Vivier <laurent@vivier.eu>
Subject: [Qemu-devel] [PATCH 22/23] target-m68k: Optimize some comparisons
Date: Tue, 25 Oct 2016 16:50:20 +0200	[thread overview]
Message-ID: <1477407021-30755-23-git-send-email-laurent@vivier.eu> (raw)
In-Reply-To: <1477407021-30755-1-git-send-email-laurent@vivier.eu>

From: Richard Henderson <rth@twiddle.net>

Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Laurent Vivier <laurent@vivier.eu>
---
 target-m68k/translate.c | 108 +++++++++++++++++++++++++++++++++++++++++++++---
 1 file changed, 102 insertions(+), 6 deletions(-)

diff --git a/target-m68k/translate.c b/target-m68k/translate.c
index 5cc5e14..b5e2995 100644
--- a/target-m68k/translate.c
+++ b/target-m68k/translate.c
@@ -771,10 +771,43 @@ static void gen_cc_cond(DisasCompare *c, DisasContext *s, int cond)
 {
     TCGv tmp, tmp2;
     TCGCond tcond;
+    CCOp op = s->cc_op;
 
-    /* TODO: Optimize compare/branch pairs rather than always flushing
-       flag state to CC_OP_FLAGS.  */
-    gen_flush_flags(s);
+    /* The CC_OP_CMP form can handle most normal comparisons directly.  */
+    if (op == CC_OP_CMP) {
+        c->g1 = c->g2 = 1;
+        c->v1 = QREG_CC_N;
+        c->v2 = QREG_CC_V;
+        switch (cond) {
+        case 2: /* HI */
+        case 3: /* LS */
+            tcond = TCG_COND_LEU;
+            goto done;
+        case 4: /* CC */
+        case 5: /* CS */
+            tcond = TCG_COND_LTU;
+            goto done;
+        case 6: /* NE */
+        case 7: /* EQ */
+            tcond = TCG_COND_EQ;
+            goto done;
+        case 10: /* PL */
+        case 11: /* MI */
+            c->g1 = c->g2 = 0;
+            c->v2 = tcg_const_i32(0);
+            c->v1 = tmp = tcg_temp_new();
+            tcg_gen_sub_i32(tmp, QREG_CC_N, QREG_CC_V);
+            /* fallthru */
+        case 12: /* GE */
+        case 13: /* LT */
+            tcond = TCG_COND_LT;
+            goto done;
+        case 14: /* GT */
+        case 15: /* LE */
+            tcond = TCG_COND_LE;
+            goto done;
+        }
+    }
 
     c->g1 = 1;
     c->g2 = 0;
@@ -785,7 +818,71 @@ static void gen_cc_cond(DisasCompare *c, DisasContext *s, int cond)
     case 1: /* F */
         c->v1 = c->v2;
         tcond = TCG_COND_NEVER;
+        goto done;
+    case 14: /* GT (!(Z || (N ^ V))) */
+    case 15: /* LE (Z || (N ^ V)) */
+        /* Logic operations clear V, which simplifies LE to (Z || N),
+           and since Z and N are co-located, this becomes a normal
+           comparison vs N.  */
+        if (op == CC_OP_LOGIC) {
+            c->v1 = QREG_CC_N;
+            tcond = TCG_COND_LE;
+            goto done;
+        }
+        break;
+    case 12: /* GE (!(N ^ V)) */
+    case 13: /* LT (N ^ V) */
+        /* Logic operations clear V, which simplifies this to N.  */
+        if (op != CC_OP_LOGIC) {
+            break;
+        }
+        /* fallthru */
+    case 10: /* PL (!N) */
+    case 11: /* MI (N) */
+        /* Several cases represent N normally.  */
+        if (op == CC_OP_ADD || op == CC_OP_SUB || op == CC_OP_LOGIC) {
+            c->v1 = QREG_CC_N;
+            tcond = TCG_COND_LT;
+            goto done;
+        }
+        break;
+    case 6: /* NE (!Z) */
+    case 7: /* EQ (Z) */
+        /* Some cases fold Z into N.  */
+        if (op == CC_OP_ADD || op == CC_OP_SUB || op == CC_OP_LOGIC) {
+            tcond = TCG_COND_EQ;
+            c->v1 = QREG_CC_N;
+            goto done;
+        }
         break;
+    case 4: /* CC (!C) */
+    case 5: /* CS (C) */
+        /* Some cases fold C into X.  */
+        if (op == CC_OP_ADD || op == CC_OP_SUB) {
+            tcond = TCG_COND_NE;
+            c->v1 = QREG_CC_X;
+            goto done;
+        }
+        /* fallthru */
+    case 8: /* VC (!V) */
+    case 9: /* VS (V) */
+        /* Logic operations clear V and C.  */
+        if (op == CC_OP_LOGIC) {
+            tcond = TCG_COND_NEVER;
+            c->v2 = c->v1;
+        }
+        break;
+    }
+
+    /* Otherwise, flush flag state to CC_OP_FLAGS.  */
+    gen_flush_flags(s);
+
+    switch (cond) {
+    case 0: /* T */
+    case 1: /* F */
+    default:
+        /* Invalid, or handled above.  */
+        abort();
     case 2: /* HI (!C && !Z) -> !(C || Z)*/
     case 3: /* LS (C || Z) */
         c->v1 = tmp = tcg_temp_new();
@@ -833,10 +930,9 @@ static void gen_cc_cond(DisasCompare *c, DisasContext *s, int cond)
         tcg_temp_free(tmp2);
         tcond = TCG_COND_LT;
         break;
-    default:
-        /* Should ever happen.  */
-        abort();
     }
+
+ done:
     if ((cond & 1) == 0) {
         tcond = tcg_invert_cond(tcond);
     }
-- 
2.7.4

  parent reply	other threads:[~2016-10-25 14:50 UTC|newest]

Thread overview: 27+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2016-10-25 14:49 [Qemu-devel] [PATCH 00/23] target-m68k: prepare to introduce 680x0 instruction set Laurent Vivier
2016-10-25 14:49 ` [Qemu-devel] [PATCH 01/23] target-m68k: fix DEBUG_DISPATCH Laurent Vivier
2016-10-25 14:50 ` [Qemu-devel] [PATCH 02/23] target-m68k: Build the opcode table only once to avoid multithreading issues Laurent Vivier
2016-10-25 14:50 ` [Qemu-devel] [PATCH 03/23] target-m68k: define m680x0 CPUs and features Laurent Vivier
2016-10-25 14:50 ` [Qemu-devel] [PATCH 04/23] target-m68k: manage scaled index Laurent Vivier
2016-10-25 14:50 ` [Qemu-devel] [PATCH 05/23] target-m68k: introduce read_imXX() functions Laurent Vivier
2016-10-25 14:50 ` [Qemu-devel] [PATCH 06/23] target-m68k: set disassembler mode to 680x0 or coldfire Laurent Vivier
2016-10-25 14:50 ` [Qemu-devel] [PATCH 07/23] target-m68k: define operand sizes Laurent Vivier
2016-10-25 14:50 ` [Qemu-devel] [PATCH 08/23] target-m68k: set PAGE_BITS to 12 for m68k Laurent Vivier
2016-10-25 14:50 ` [Qemu-devel] [PATCH 09/23] target-m68k: REG() macro cleanup Laurent Vivier
2016-10-25 14:50 ` [Qemu-devel] [PATCH 10/23] target-m68k: allow to update flags with operation on words and bytes Laurent Vivier
2016-10-25 14:50 ` [Qemu-devel] [PATCH 11/23] target-m68k: Replace helper_xflag_lt with setcond Laurent Vivier
2016-10-25 14:50 ` [Qemu-devel] [PATCH 12/23] target-m68k: remove m68k_cpu_exec_enter() and m68k_cpu_exec_exit() Laurent Vivier
2016-10-25 14:50 ` [Qemu-devel] [PATCH 13/23] target-m68k: update move to/from ccr/sr Laurent Vivier
2016-10-25 14:50 ` [Qemu-devel] [PATCH 14/23] target-m68k: don't update cc_dest in helpers Laurent Vivier
2016-10-25 14:50 ` [Qemu-devel] [PATCH 15/23] target-m68k: update CPU flags management Laurent Vivier
2016-10-25 14:50 ` [Qemu-devel] [PATCH 16/23] target-m68k: Print flags properly Laurent Vivier
2016-10-25 14:50 ` [Qemu-devel] [PATCH 17/23] target-m68k: Some fixes to SR and flags management Laurent Vivier
2016-10-25 14:50 ` [Qemu-devel] [PATCH 18/23] target-m68k: Remove incorrect clearing of cc_x Laurent Vivier
2016-10-25 14:50 ` [Qemu-devel] [PATCH 19/23] target-m68k: Reorg flags handling Laurent Vivier
2016-10-25 14:50 ` [Qemu-devel] [PATCH 20/23] target-m68k: Introduce DisasCompare Laurent Vivier
2016-10-25 14:50 ` [Qemu-devel] [PATCH 21/23] target-m68k: Use setcond for scc Laurent Vivier
2016-10-25 14:50 ` Laurent Vivier [this message]
2016-10-25 17:41   ` [Qemu-devel] [PATCH 22/23] target-m68k: Optimize some comparisons Richard Henderson
2016-10-25 14:50 ` [Qemu-devel] [PATCH 23/23] target-m68k: Optimize gen_flush_flags Laurent Vivier
2016-10-25 17:45 ` [Qemu-devel] [PATCH 00/23] target-m68k: prepare to introduce 680x0 instruction set Richard Henderson
2016-10-25 17:53   ` Laurent Vivier

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