From: "Kani, Toshimitsu" <toshi.kani@hpe.com>
To: "dan.j.williams@intel.com" <dan.j.williams@intel.com>,
"dave.jiang@intel.com" <dave.jiang@intel.com>,
"vinod.koul@intel.com" <vinod.koul@intel.com>
Cc: "dmaengine@vger.kernel.org" <dmaengine@vger.kernel.org>,
"hch@infradead.org" <hch@infradead.org>,
"linux-nvdimm@lists.01.org" <linux-nvdimm@lists.01.org>
Subject: Re: [PATCH v7 9/9] libnvdimm: Add DMA based blk-mq pmem driver
Date: Thu, 31 Aug 2017 22:13:18 +0000 [thread overview]
Message-ID: <1504216996.2042.182.camel@hpe.com> (raw)
In-Reply-To: <150412658373.69288.2856155675209269488.stgit@djiang5-desk3.ch.intel.com>
On Wed, 2017-08-30 at 13:56 -0700, Dave Jiang wrote:
:
+static int pmem_attach_disk(struct device *dev,
> + struct nd_namespace_common *ndns)
> +{
> + struct pmem_device *pmem;
> + int rc;
> + struct dma_chan *chan = NULL;
> + int has_dma;
> +
> + pmem = pmem_core_setup_pmem(dev, ndns);
> + if (!pmem)
> + return -ENXIO;
> +
> + chan = dma_find_channel(DMA_MEMCPY_SG);
> + if (!chan)
> + dev_warn(dev, "Forced back to CPU, no DMA\n");
I just tested this series on a Haswell system. The above warning
messages was shown during boot-up (is this expected?), but it did not
appear to switch back to CPU. Initial IO requests to pmem (mkfs) hit
the WARN_ON_ONCE() below. pmem->sg_allocated is zero since it was not
initialized (has_dma was set to 0).
[ 897.147527] WARNING: CPU: 23 PID: 707 at
drivers/nvdimm/pmem_dma.c:171 pmem_handle_cmd_dma+0x675/0x710
It then displayed seemed-forever-repeated error messages below.
ioatdma 0000:80:04.7: ioat_timer_event: Channel halted (1)
ioatdma 0000:80:04.7: Errors:
ioatdma 0000:80:04.7: Err(0): DMA Transfer Source Address Error
ioatdma 0000:80:04.7: Reset channel...
ioatdma 0000:80:04.7: Restart channel...
ioatdma 0000:80:04.7: ioat_timer_event: Channel halted (1000)
ioatdma 0000:80:04.7: Errors:
ioatdma 0000:80:04.7: Err(12): Completion Address Error
ioatdma 0000:80:04.7: Reset channel...
ioatdma 0000:80:04.7: Restart channel...
ioatdma 0000:80:04.7: ioat_timer_event: Channel halted (1000)
:
Any thoughts? Also, how do I choose the mode between CPU and DMA?
Thanks!
-Toshi
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next prev parent reply other threads:[~2017-08-31 22:10 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-08-30 20:55 [PATCH v7 0/9] libnvdimm: add DMA supported blk-mq pmem driver Dave Jiang
2017-08-30 20:55 ` [PATCH v7 1/9] dmaengine: ioatdma: revert 7618d035 to allow sharing of DMA channels Dave Jiang
2017-08-30 20:55 ` [PATCH v7 2/9] dmaengine: Add DMA_MEMCPY_SG transaction op Dave Jiang
2017-08-30 20:55 ` [PATCH v7 3/9] dmaengine: ioatdma: dma_prep_memcpy_sg support Dave Jiang
2017-08-30 20:55 ` [PATCH v7 4/9] dmaengine: add function to provide per descriptor xfercap for dma engine Dave Jiang
2017-08-30 20:56 ` [PATCH v7 5/9] dmaengine: add SG support to dmaengine_unmap Dave Jiang
2017-08-30 20:56 ` [PATCH v7 6/9] dmaengine: provide number of available channels Dave Jiang
2017-08-30 20:56 ` [PATCH v7 7/9] libnvdimm: remove definition of REQ_FLUSH Dave Jiang
2017-08-30 20:56 ` [PATCH v7 8/9] libnvdimm: move common function for pmem to pmem_core Dave Jiang
2017-08-30 20:56 ` [PATCH v7 9/9] libnvdimm: Add DMA based blk-mq pmem driver Dave Jiang
2017-08-31 22:13 ` Kani, Toshimitsu [this message]
2017-08-31 23:37 ` Dave Jiang
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