Re: [PATCH 00/20] Add support for GuC-based SLPC

From: "Szwichtenberg, Radoslaw" <radoslaw.szwichtenberg@intel.com>
To: "intel-gfx@lists.freedesktop.org"
	<intel-gfx@lists.freedesktop.org>,
	"Kamble, Sagar A" <sagar.a.kamble@intel.com>
Cc: "Beuchat, Marc" <marc.beuchat@intel.com>,
	"Vetter, Daniel" <daniel.vetter@intel.com>
Subject: Re: [PATCH 00/20] Add support for GuC-based SLPC
Date: Tue, 12 Sep 2017 08:39:13 +0000	[thread overview]
Message-ID: <1505205550.21576.24.camel@intel.com> (raw)
In-Reply-To: <1504250723-32018-1-git-send-email-sagar.a.kamble@intel.com>

On Fri, 2017-09-01 at 12:55 +0530, Sagar Arun Kamble wrote:
> SLPC (Single Loop Power Controller) is a replacement for some host-based
> power management features. The SLPC implementation runs in GuC firmware.
> This series has been tested with SKL/APL/KBL GuC firmware v9 and v10
> which are yet to be released on 01.org.
> 
> The graphics power management features in SLPC are called GTPERF,
> BALANCER, and DCC.
> 1. GTPERF is a combination of DFPS (Dynamic FPS) and Turbo. DFPS adjusts
> requested graphics frequency to maintain target framerate. Turbo adjusts
> requested graphics frequency to maintain target GT busyness.
> 2. BALANCER adjusts balance between power budgets for IA and GT in power
> limited scenarios.
> 3. DCC (Duty Cycle Control) adjusts requested graphics frequency and stalls
> guc-scheduler to maintain actual graphics frequency in efficient range.
> 
> This series activates GTPERF Turbo and BALANCER in GuC SLPC.
> Patch to enable SLPC by default on platforms having support is removed
> from this series as there are following new changes to be added in future
> before we enable GuC/SLPC by default:
> 1. Link waitboost with SLPC.
> 2. Handle CPG as part of SLPC.
> 3. IA p-state logic update with GuC submission.
> 
> In order to enable CI/PnP testing of SLPC and to avoid frequent
> rebase, this series should be safe for merge with feature in disabled
> state.
> 
> v2: Addressed review comments on v1. Removed patch to enable SLPC by
>     default.
> 
> v3: Addressed WARNING in igt@drv_module_reload_basic flagged by trybot BAT.
>     Added change for sanitizing GT PM during reset. Added separate patch
>     for sysfs interface to know HW requested frequency. Also, earlier
>     patches did not go as series hence were not correctly picked up by BAT.
> 
> v4: Changes to multiple patches. CI BAT is passing. Performance run on SKL
>     GT2 done and shows perf at parity with Host Turbo. For BXT, SLPC
>     improves performance when GuC is enabled compared to Host Turbo.
>     This series keeps only support of 9.18 firmware for better readability.
>     If needed, other SLPC interfaces for different GuC version will be
>     added later.
> 
> v5: This series incorporates feedback from code reviews on earlier series
>     and adds following new changes:
> 	1. More changes for separation of RPS and RC6 handling for Gen9.
> 	2. Tied up SLPC enabling with GuC load/GuC submission sequence.
> 	3. SLPC structures are defined explicitly for event input/output.
> 	4. Definition of SLPC parameter control and task control functions
> 	   agnostic to the underlying param definitions as they might
> 	   change with GuC versions and prepared helpers for common tasks.
> 	5. Transition of i915 overrides done through host to guc events
> 	   to shared data and single reset event.
> 	6. Handling SLPC status post reset through shared memory.
> 	7. Derived helpers for setting frequency limits.
> 	8. Removed sysfs interface to know RPNSWREQ as it is available in
> 	   debugfs interface i915_frequency_info.
> 	9. Simple igt test to verify SLPC configuration by i915 in various
> 	   driver scenarios is prepared.
> 
> v6: This series adds following new changes:
> 	1. Updated intel_guc_send for SLPC to receive output data from GuC.
> 	2. Added task overrides and min frequency overrides in intel_slpc_init.
> 	   min frequency is set to Rpe.
> 	3. New debugfs interface added to set/unset/read SLPC parameters
> 	   other than tasks and frequencies. SLPC reset post parameter update
> 	   added.
> 	4. SLPC parameters persist as part of i915-GuC shared data hence not
> 	   overriding frequency limits while re-enabling SLPC.
> 	5. Other minor fixes to clear pm_rps_events, clflush the shared data.
> 
> v7: This series adds following new changes:
> 	1. Reordered patches. SLPC communication interfaces (structures and
> 	   functions) are pulled into patches earlier in the series.
> 	2. Eliminated dependency on i915.enable_slpc at various functions where
> 	   rps_enabled is available.
> 	3. s/i915_ggtt_offset/guc_ggtt_offset and sanitization of parameter
> 	   in intel_uc_sanitize_options.
> 
> v8: Activated Balancer. Changed prototype of SLPC functions to accept
>     struct intel_slpc as parameter instead of drm_i915_private.
> 
> VIZ-6889, VIZ-6890
> 
> Cc: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Daniel Vetter <daniel.vetter@intel.com>
> Cc: Beuchat, Marc <marc.beuchat@intel.com>
> Cc: Radoslaw Szwichtenberg <radoslaw.szwichtenberg@intel.com>
> Cc: Jeff McGee <jeff.mcgee@intel.com>
> Cc: Arkadiusz Hiler <arkadiusz.hiler@intel.com>
> Cc: Oscar Mateo <oscar.mateo@intel.com>
> Cc: Michał Winiarski <michal.winiarski@intel.com>

I did enable SLPC on my machine and looks like everything is working fine. I
will be spending more time reviewing whole series and also running some tests on
my KBL to see if there are no functional problems.

-Radek
Acked-by: Radoslaw Szwichtenberg <radoslaw.szwichtenberg@intel.com>
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