[PATCH 14/22] drm/i915/icl: WaEnableStateCacheRedirectToCS

From: Oscar Mateo <oscar.mateo@intel.com>
To: intel-gfx@lists.freedesktop.org
Subject: [PATCH 14/22] drm/i915/icl: WaEnableStateCacheRedirectToCS
Date: Fri,  6 Apr 2018 15:25:10 -0700	[thread overview]
Message-ID: <1523053518-20827-14-git-send-email-oscar.mateo@intel.com> (raw)
In-Reply-To: <1523053518-20827-1-git-send-email-oscar.mateo@intel.com>

Redirects the state cache to the CS Command buffer section for
performance reasons.

v2: Rebased

Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h        | 1 +
 drivers/gpu/drm/i915/intel_engine_cs.c | 4 ++++
 2 files changed, 5 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index f2ae3cf..3bec6b1 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7150,6 +7150,7 @@ enum {
 #define  DISABLE_PIXEL_MASK_CAMMING		(1<<14)
 
 #define GEN9_SLICE_COMMON_ECO_CHICKEN1		_MMIO(0x731c)
+#define   GEN11_STATE_CACHE_REDIRECT_TO_CS	(1 << 11)
 
 #define GEN7_L3SQCREG1				_MMIO(0xB010)
 #define  VLV_B0_WA_L3SQCREG1_VALUE		0x00D30000
diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c
index 8337301..d0c382e 100644
--- a/drivers/gpu/drm/i915/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/intel_engine_cs.c
@@ -1495,6 +1495,10 @@ static int icl_init_workarounds(struct intel_engine_cs *engine)
 		WA_SET_BIT_MASKED(GEN7_ROW_CHICKEN2,
 				  GEN11_TDL_CLOCK_GATING_FIX_DISABLE);
 
+	/* WaEnableStateCacheRedirectToCS:icl */
+	WA_SET_BIT_MASKED(GEN9_SLICE_COMMON_ECO_CHICKEN1,
+			  GEN11_STATE_CACHE_REDIRECT_TO_CS);
+
 	/* WaSendPushConstantsFromMMIO:icl */
 	ret = wa_ring_whitelist_reg(engine, COMMON_SLICE_CHICKEN2);
 	if (ret)
-- 
1.9.1

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