Re: [PATCH V2] drm/i915: Use I915_MAP_WC for execlists context buffer on the platforms without LLC

From: Chris Wilson <chris@chris-wilson.co.uk>
To: Zhao Yakui <yakui.zhao@intel.com>, intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH V2] drm/i915: Use I915_MAP_WC for execlists context buffer on the platforms without LLC
Date: Fri, 22 Jun 2018 07:26:07 +0100	[thread overview]
Message-ID: <152964876785.11773.15377952246210335262@mail.alporthouse.com> (raw)
In-Reply-To: <1529647750-25008-1-git-send-email-yakui.zhao@intel.com>

Quoting Zhao Yakui (2018-06-22 07:09:10)
> Under execlists mode the context buffer is allocated in global Gtt region.
> The I915_MAP_WB type is used to map the buffer so that the driver can
> initialize the context buffer.(Ring reg, Context Ctrl reg and so on).
> And then __context_pin is called to flush back corresponding contents.
> In fact as it also tries to update context buffer (Ring Tail offset)
> before writing the ELSP port, it has no explicit cache flsuh.Maybe it is
> handled by HW. But this is quite confusing as BXT has no LLC. So the WC
> is used to map the context buffer on the platform without LLC and the
> update of context buffer is writen into phys page directly. It will
> be safer.
> 
> V1->V2: Remove the dirty flag of execlists state buffer and one minor
> typo in commit log

The object's pages are still dirty, so why? It's not about CPU cache
dirt, here it is about whether the pages differ from any potential
swapcache.

I was anticipating there would be some type conflict with
engine->pinned_default_state, but that just happens to work out
correctly... so long as there is always a retirement during load and we
park before any reset. Hmm.
-Chris
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