From: Madhav Chauhan <madhav.chauhan@intel.com>
To: intel-gfx@lists.freedesktop.org
Cc: jani.nikula@intel.com, komala.b.rangappa@intel.com,
rodrigo.vivi@intel.com
Subject: [PATCH v6 07/20] drm/i915/icl: Define TA_TIMING_PARAM registers
Date: Sun, 16 Sep 2018 16:23:30 +0530 [thread overview]
Message-ID: <1537095223-5184-8-git-send-email-madhav.chauhan@intel.com> (raw)
In-Reply-To: <1537095223-5184-1-git-send-email-madhav.chauhan@intel.com>
This patch defines DSI_TA_TIMING_PARAM and
DPHY_TA_TIMING_PARAM registers used in
dphy programming.
v2: Changes (Jani N)
- Define mask/shift for bitfields
- Use bitfields name as per BSPEC
- Define remaining bitfields
Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 23 +++++++++++++++++++++++
1 file changed, 23 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 6c8999d..b27d0c1 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -10343,6 +10343,29 @@ enum skl_power_gate {
#define HS_EXIT_MASK (0x7 << 0)
#define HS_EXIT_SHIFT 0
+#define _DPHY_TA_TIMING_PARAM_0 0x162188
+#define _DPHY_TA_TIMING_PARAM_1 0x6c188
+#define DPHY_TA_TIMING_PARAM(port) _MMIO_PORT(port, \
+ _DPHY_TA_TIMING_PARAM_0,\
+ _DPHY_TA_TIMING_PARAM_1)
+#define _DSI_TA_TIMING_PARAM_0 0x6b098
+#define _DSI_TA_TIMING_PARAM_1 0x6b898
+#define DSI_TA_TIMING_PARAM(port) _MMIO_PORT(port, \
+ _DSI_TA_TIMING_PARAM_0,\
+ _DSI_TA_TIMING_PARAM_1)
+#define TA_SURE_OVERRIDE (1 << 31)
+#define TA_SURE(x) ((x) << 16)
+#define TA_SURE_MASK (0x1f << 16)
+#define TA_SURE_SHIFT 16
+#define TA_GO_OVERRIDE (1 << 15)
+#define TA_GO(x) ((x) << 8)
+#define TA_GO_MASK (0xf << 8)
+#define TA_GO_SHIFT 8
+#define TA_GET_OVERRIDE (1 << 7)
+#define TA_GET(x) ((x) << 0)
+#define TA_GET_MASK (0xf << 0)
+#define TA_GET_SHIFT 0
+
/* bits 31:0 */
#define _MIPIA_DBI_BW_CTRL (dev_priv->mipi_mmio_base + 0xb084)
#define _MIPIC_DBI_BW_CTRL (dev_priv->mipi_mmio_base + 0xb884)
--
2.7.4
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next prev parent reply other threads:[~2018-09-16 11:04 UTC|newest]
Thread overview: 29+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-09-16 10:53 [PATCH v6 00/20] ICELAKE DSI DRIVER Madhav Chauhan
2018-09-16 10:53 ` [PATCH v6 01/20] drm/i915/icl: Configure lane sequencing of combo phy transmitter Madhav Chauhan
2018-09-16 10:53 ` [PATCH v6 02/20] drm/i915/icl: DSI vswing programming sequence Madhav Chauhan
2018-09-16 10:53 ` [PATCH v6 03/20] drm/i915/icl: Enable DDI Buffer Madhav Chauhan
2018-09-16 10:53 ` [PATCH v6 04/20] drm/i915/icl: Program T_INIT_MASTER registers Madhav Chauhan
2018-09-16 10:53 ` [PATCH v6 05/20] drm/i915/icl: Define data/clock lanes dphy timing registers Madhav Chauhan
2018-09-16 10:53 ` [PATCH v6 06/20] drm/i915/icl: Program DSI clock and data lane timing params Madhav Chauhan
2018-09-26 12:59 ` Jani Nikula
2018-09-26 13:08 ` Chauhan, Madhav
2018-09-16 10:53 ` Madhav Chauhan [this message]
2018-09-26 13:06 ` [PATCH v6 07/20] drm/i915/icl: Define TA_TIMING_PARAM registers Jani Nikula
2018-09-16 10:53 ` [PATCH v6 08/20] drm/i915/icl: Program " Madhav Chauhan
2018-09-16 10:53 ` [PATCH v6 09/20] drm/i915/icl: Get DSI transcoder for a given port Madhav Chauhan
2018-09-16 10:53 ` [PATCH v6 10/20] drm/i915/icl: Add macros for MMIO of DSI transcoder registers Madhav Chauhan
2018-09-16 10:53 ` [PATCH v6 11/20] drm/i915/icl: Define TRANS_DSI_FUNC_CONF register Madhav Chauhan
2018-09-16 10:53 ` [PATCH v6 12/20] drm/i915/icl: Configure DSI transcoders Madhav Chauhan
2018-09-16 10:53 ` [PATCH v6 13/20] drm/i915/icl: Define TRANS_DDI_FUNC_CTL DSI registers Madhav Chauhan
2018-09-16 10:53 ` [PATCH v6 14/20] drm/i915/icl: Program TRANS_DDI_FUNC_CTL registers Madhav Chauhan
2018-09-16 10:53 ` [PATCH v6 15/20] drm/i915/icl: Define DSI transcoder timing registers Madhav Chauhan
2018-09-16 10:53 ` [PATCH v6 16/20] drm/i915/icl: Configure DSI transcoder timings Madhav Chauhan
2018-09-16 10:53 ` [PATCH v6 17/20] drm/i915/icl: Define TRANS_CONF register for DSI Madhav Chauhan
2018-09-16 10:53 ` [PATCH v6 18/20] drm/i915/icl: Enable DSI transcoders Madhav Chauhan
2018-09-16 10:53 ` [PATCH v6 19/20] drm/i915/icl: Define DSI panel programming registers Madhav Chauhan
2018-09-16 10:53 ` [PATCH v6 20/20] drm/i915/icl: Set max return packet size for DSI panel Madhav Chauhan
2018-09-16 18:16 ` ✗ Fi.CI.CHECKPATCH: warning for ICELAKE DSI DRIVER (rev6) Patchwork
2018-09-16 18:23 ` ✗ Fi.CI.SPARSE: " Patchwork
2018-09-16 18:34 ` ✗ Fi.CI.BAT: failure " Patchwork
2018-09-17 10:29 ` ✓ Fi.CI.BAT: success " Patchwork
2018-09-17 11:32 ` ✓ Fi.CI.IGT: " Patchwork
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