From: fabrizio.castro@bp.renesas.com (Fabrizio Castro)
To: cip-dev@lists.cip-project.org
Subject: [cip-dev] [PATCH/RFC 4.19.y-cip 21/41] pinctrl: sh-pfc: r8a7796: Add I2C{0, 3, 5} pins, groups and functions
Date: Wed, 28 Aug 2019 12:21:48 +0100 [thread overview]
Message-ID: <1566991328-25476-22-git-send-email-fabrizio.castro@bp.renesas.com> (raw)
In-Reply-To: <1566991328-25476-1-git-send-email-fabrizio.castro@bp.renesas.com>
From: Takeshi Kihara <takeshi.kihara.df@renesas.com>
commit 8d7bcad65ef390ef9efd4b3d3fd18dc2a08f2a14 upstream.
This patch adds I2C{0,3,5} pins, groups and functions to the R8A7796 SoC.
These pins are physically muxed with other pins. Therefore, setup of
MOD_SEL is needed for exclusive control with other pins.
Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
Signed-off-by: Ulrich Hecht <uli+renesas@fpond.eu>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
---
drivers/pinctrl/sh-pfc/pfc-r8a7796.c | 98 ++++++++++++++++++++++++++++--------
1 file changed, 77 insertions(+), 21 deletions(-)
diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7796.c b/drivers/pinctrl/sh-pfc/pfc-r8a7796.c
index 1577620..5ab1b60 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a7796.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a7796.c
@@ -557,6 +557,9 @@ MOD_SEL0_4_3 MOD_SEL1_4 \
FM(DU_DOTCLKIN0) FM(DU_DOTCLKIN1) FM(DU_DOTCLKIN2) \
FM(TMS) FM(TDO) FM(ASEBRK) FM(MLB_REF) FM(TDI) FM(TCK) FM(TRST) FM(EXTALR)
+#define PINMUX_PHYS \
+ FM(SCL0) FM(SDA0) FM(SCL3) FM(SDA3) FM(SCL5) FM(SDA5)
+
enum {
PINMUX_RESERVED = 0,
@@ -582,6 +585,7 @@ enum {
PINMUX_IPSR
PINMUX_MOD_SELS
PINMUX_STATIC
+ PINMUX_PHYS
PINMUX_MARK_END,
#undef F_
#undef FM
@@ -618,13 +622,15 @@ static const u16 pinmux_data[] = {
PINMUX_IPSR_MSEL(IP0_15_12, MSIOF2_SCK_C, SEL_MSIOF2_2),
PINMUX_IPSR_MSEL(IP0_15_12, TX4_A, SEL_SCIF4_0),
- PINMUX_IPSR_MSEL(IP0_19_16, AVB_AVTP_MATCH_A, SEL_ETHERAVB_0),
- PINMUX_IPSR_MSEL(IP0_19_16, MSIOF2_RXD_C, SEL_MSIOF2_2),
- PINMUX_IPSR_MSEL(IP0_19_16, CTS4_N_A, SEL_SCIF4_0),
+ PINMUX_IPSR_PHYS_MSEL(IP0_19_16, AVB_AVTP_MATCH_A, I2C_SEL_5_0, SEL_ETHERAVB_0),
+ PINMUX_IPSR_PHYS_MSEL(IP0_19_16, MSIOF2_RXD_C, I2C_SEL_5_0, SEL_MSIOF2_2),
+ PINMUX_IPSR_PHYS_MSEL(IP0_19_16, CTS4_N_A, I2C_SEL_5_0, SEL_SCIF4_0),
+ PINMUX_IPSR_PHYS(IP0_19_16, SCL5, I2C_SEL_5_1),
- PINMUX_IPSR_MSEL(IP0_23_20, AVB_AVTP_CAPTURE_A, SEL_ETHERAVB_0),
- PINMUX_IPSR_MSEL(IP0_23_20, MSIOF2_TXD_C, SEL_MSIOF2_2),
- PINMUX_IPSR_MSEL(IP0_23_20, RTS4_N_A, SEL_SCIF4_0),
+ PINMUX_IPSR_PHYS_MSEL(IP0_23_20, AVB_AVTP_CAPTURE_A, I2C_SEL_5_0, SEL_ETHERAVB_0),
+ PINMUX_IPSR_PHYS_MSEL(IP0_23_20, MSIOF2_TXD_C, I2C_SEL_5_0, SEL_MSIOF2_2),
+ PINMUX_IPSR_PHYS_MSEL(IP0_23_20, RTS4_N_A, I2C_SEL_5_0, SEL_SCIF4_0),
+ PINMUX_IPSR_PHYS(IP0_23_20, SDA5, I2C_SEL_5_1),
PINMUX_IPSR_GPSR(IP0_27_24, IRQ0),
PINMUX_IPSR_GPSR(IP0_27_24, QPOLB),
@@ -676,14 +682,16 @@ static const u16 pinmux_data[] = {
PINMUX_IPSR_MSEL(IP1_19_16, VI4_DATA6_B, SEL_VIN4_1),
PINMUX_IPSR_MSEL(IP1_19_16, IECLK_B, SEL_IEBUS_1),
- PINMUX_IPSR_MSEL(IP1_23_20, PWM1_A, SEL_PWM1_0),
- PINMUX_IPSR_MSEL(IP1_23_20, HRX3_D, SEL_HSCIF3_3),
- PINMUX_IPSR_MSEL(IP1_23_20, VI4_DATA7_B, SEL_VIN4_1),
- PINMUX_IPSR_MSEL(IP1_23_20, IERX_B, SEL_IEBUS_1),
+ PINMUX_IPSR_PHYS_MSEL(IP1_23_20, PWM1_A, I2C_SEL_3_0, SEL_PWM1_0),
+ PINMUX_IPSR_PHYS_MSEL(IP1_23_20, HRX3_D, I2C_SEL_3_0, SEL_HSCIF3_3),
+ PINMUX_IPSR_PHYS_MSEL(IP1_23_20, VI4_DATA7_B, I2C_SEL_3_0, SEL_VIN4_1),
+ PINMUX_IPSR_PHYS_MSEL(IP1_23_20, IERX_B, I2C_SEL_3_0, SEL_IEBUS_1),
+ PINMUX_IPSR_PHYS(IP0_23_20, SCL3, I2C_SEL_3_1),
- PINMUX_IPSR_MSEL(IP1_27_24, PWM2_A, SEL_PWM2_0),
- PINMUX_IPSR_MSEL(IP1_27_24, HTX3_D, SEL_HSCIF3_3),
- PINMUX_IPSR_MSEL(IP1_27_24, IETX_B, SEL_IEBUS_1),
+ PINMUX_IPSR_PHYS_MSEL(IP1_27_24, PWM2_A, I2C_SEL_3_0, SEL_PWM2_0),
+ PINMUX_IPSR_PHYS_MSEL(IP1_27_24, HTX3_D, I2C_SEL_3_0, SEL_HSCIF3_3),
+ PINMUX_IPSR_PHYS_MSEL(IP1_27_24, IETX_B, I2C_SEL_3_0, SEL_IEBUS_1),
+ PINMUX_IPSR_PHYS(IP1_27_24, SDA3, I2C_SEL_3_1),
PINMUX_IPSR_GPSR(IP1_31_28, A0),
PINMUX_IPSR_GPSR(IP1_31_28, LCDOUT16),
@@ -1116,13 +1124,15 @@ static const u16 pinmux_data[] = {
PINMUX_IPSR_MSEL(IP11_15_12, NFDATA15_A, SEL_NDFC_0),
PINMUX_IPSR_MSEL(IP11_15_12, SDA2_B, SEL_I2C2_1),
- PINMUX_IPSR_GPSR(IP11_19_16, SD1_CD),
- PINMUX_IPSR_MSEL(IP11_19_16, NFRB_N_A, SEL_NDFC_0),
- PINMUX_IPSR_MSEL(IP11_19_16, SIM0_CLK_B, SEL_SIMCARD_1),
+ PINMUX_IPSR_MSEL(IP11_19_16, SD1_CD, I2C_SEL_0_0),
+ PINMUX_IPSR_PHYS_MSEL(IP11_19_16, NFRB_N_A, I2C_SEL_0_0, SEL_NDFC_0),
+ PINMUX_IPSR_PHYS_MSEL(IP11_19_16, SIM0_CLK_B, I2C_SEL_0_0, SEL_SIMCARD_1),
+ PINMUX_IPSR_PHYS(IP11_19_16, SCL0, I2C_SEL_0_1),
- PINMUX_IPSR_GPSR(IP11_23_20, SD1_WP),
- PINMUX_IPSR_MSEL(IP11_23_20, NFCE_N_A, SEL_NDFC_0),
- PINMUX_IPSR_MSEL(IP11_23_20, SIM0_D_B, SEL_SIMCARD_1),
+ PINMUX_IPSR_MSEL(IP11_23_20, SD1_WP, I2C_SEL_0_0),
+ PINMUX_IPSR_PHYS_MSEL(IP11_23_20, NFCE_N_A, I2C_SEL_0_0, SEL_NDFC_0),
+ PINMUX_IPSR_PHYS_MSEL(IP11_23_20, SIM0_D_B, I2C_SEL_0_0, SEL_SIMCARD_1),
+ PINMUX_IPSR_PHYS(IP11_23_20, SDA0, I2C_SEL_0_1),
PINMUX_IPSR_GPSR(IP11_27_24, SCK0),
PINMUX_IPSR_MSEL(IP11_27_24, HSCK1_B, SEL_HSCIF1_1),
@@ -2348,6 +2358,15 @@ static const unsigned int hscif4_data_b_mux[] = {
};
/* - I2C -------------------------------------------------------------------- */
+static const unsigned int i2c0_pins[] = {
+ /* SCL, SDA */
+ RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15),
+};
+
+static const unsigned int i2c0_mux[] = {
+ SCL0_MARK, SDA0_MARK,
+};
+
static const unsigned int i2c1_a_pins[] = {
/* SDA, SCL */
RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 10),
@@ -2376,6 +2395,25 @@ static const unsigned int i2c2_b_pins[] = {
static const unsigned int i2c2_b_mux[] = {
SDA2_B_MARK, SCL2_B_MARK,
};
+
+static const unsigned int i2c3_pins[] = {
+ /* SCL, SDA */
+ RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8),
+};
+
+static const unsigned int i2c3_mux[] = {
+ SCL3_MARK, SDA3_MARK,
+};
+
+static const unsigned int i2c5_pins[] = {
+ /* SCL, SDA */
+ RCAR_GP_PIN(2, 13), RCAR_GP_PIN(2, 14),
+};
+
+static const unsigned int i2c5_mux[] = {
+ SCL5_MARK, SDA5_MARK,
+};
+
static const unsigned int i2c6_a_pins[] = {
/* SDA, SCL */
RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11),
@@ -4125,7 +4163,7 @@ static const unsigned int vin5_clk_mux[] = {
};
static const struct {
- struct sh_pfc_pin_group common[307];
+ struct sh_pfc_pin_group common[310];
struct sh_pfc_pin_group automotive[33];
} pinmux_groups = {
.common = {
@@ -4198,10 +4236,13 @@ static const struct {
SH_PFC_PIN_GROUP(hscif4_clk),
SH_PFC_PIN_GROUP(hscif4_ctrl),
SH_PFC_PIN_GROUP(hscif4_data_b),
+ SH_PFC_PIN_GROUP(i2c0),
SH_PFC_PIN_GROUP(i2c1_a),
SH_PFC_PIN_GROUP(i2c1_b),
SH_PFC_PIN_GROUP(i2c2_a),
SH_PFC_PIN_GROUP(i2c2_b),
+ SH_PFC_PIN_GROUP(i2c3),
+ SH_PFC_PIN_GROUP(i2c5),
SH_PFC_PIN_GROUP(i2c6_a),
SH_PFC_PIN_GROUP(i2c6_b),
SH_PFC_PIN_GROUP(i2c6_c),
@@ -4630,6 +4671,10 @@ static const char * const hscif4_groups[] = {
"hscif4_data_b",
};
+static const char * const i2c0_groups[] = {
+ "i2c0",
+};
+
static const char * const i2c1_groups[] = {
"i2c1_a",
"i2c1_b",
@@ -4640,6 +4685,14 @@ static const char * const i2c2_groups[] = {
"i2c2_b",
};
+static const char * const i2c3_groups[] = {
+ "i2c3",
+};
+
+static const char * const i2c5_groups[] = {
+ "i2c5",
+};
+
static const char * const i2c6_groups[] = {
"i2c6_a",
"i2c6_b",
@@ -4968,7 +5021,7 @@ static const char * const vin5_groups[] = {
};
static const struct {
- struct sh_pfc_function common[45];
+ struct sh_pfc_function common[48];
struct sh_pfc_function automotive[6];
} pinmux_functions = {
.common = {
@@ -4984,8 +5037,11 @@ static const struct {
SH_PFC_FUNCTION(hscif2),
SH_PFC_FUNCTION(hscif3),
SH_PFC_FUNCTION(hscif4),
+ SH_PFC_FUNCTION(i2c0),
SH_PFC_FUNCTION(i2c1),
SH_PFC_FUNCTION(i2c2),
+ SH_PFC_FUNCTION(i2c3),
+ SH_PFC_FUNCTION(i2c5),
SH_PFC_FUNCTION(i2c6),
SH_PFC_FUNCTION(intc_ex),
SH_PFC_FUNCTION(msiof0),
--
2.7.4
next prev parent reply other threads:[~2019-08-28 11:21 UTC|newest]
Thread overview: 55+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-08-28 11:21 [cip-dev] [PATCH/RFC 4.19.y-cip 00/41] Fast forward sh-pfc Fabrizio Castro
2019-08-28 11:21 ` [cip-dev] [PATCH/RFC 4.19.y-cip 01/41] pinctrl: sh-pfc: Print actual field width for variable-width fields Fabrizio Castro
2019-08-28 11:21 ` [cip-dev] [PATCH/RFC 4.19.y-cip 02/41] pinctrl: sh-pfc: Validate pinmux tables at runtime when debugging Fabrizio Castro
2019-08-28 11:21 ` [cip-dev] [PATCH/RFC 4.19.y-cip 03/41] pinctrl: sh-pfc: Add physical pin multiplexing helper macros Fabrizio Castro
2019-08-28 11:21 ` [cip-dev] [PATCH/RFC 4.19.y-cip 04/41] pinctrl: sh-pfc: Validate pins/marks in pin groups at build time Fabrizio Castro
2019-08-28 11:21 ` [cip-dev] [PATCH/RFC 4.19.y-cip 05/41] pinctrl: sh-pfc: Make pinmux_cfg_reg.var_field_width[] variable-length Fabrizio Castro
2019-08-28 11:21 ` [cip-dev] [PATCH/RFC 4.19.y-cip 06/41] pinctrl: sh-pfc: Validate fixed-size field widths at build time Fabrizio Castro
2019-08-28 11:21 ` [cip-dev] [PATCH/RFC 4.19.y-cip 07/41] pinctrl: sh-pfc: Absorb enum IDs in PINMUX_CFG_REG() macro Fabrizio Castro
2019-08-29 8:09 ` Pavel Machek
2019-08-29 9:31 ` Fabrizio Castro
2019-08-28 11:21 ` [cip-dev] [PATCH/RFC 4.19.y-cip 08/41] pinctrl: sh-pfc: Absorb enum IDs in PINMUX_CFG_REG_VAR() macro Fabrizio Castro
2019-08-28 11:21 ` [cip-dev] [PATCH/RFC 4.19.y-cip 09/41] pinctrl: sh-pfc: Absorb enum IDs in PINMUX_DATA_REG() macro Fabrizio Castro
2019-08-28 11:21 ` [cip-dev] [PATCH/RFC 4.19.y-cip 10/41] pinctrl: sh-pfc: Validate enum IDs for regs with fixed-width fields Fabrizio Castro
2019-08-28 11:21 ` [cip-dev] [PATCH/RFC 4.19.y-cip 11/41] pinctrl: sh-pfc: Validate enum IDs for regs with variable-width fields Fabrizio Castro
2019-08-28 11:21 ` [cip-dev] [PATCH/RFC 4.19.y-cip 12/41] pinctrl: sh-pfc: Improve PINMUX_IPSR_PHYS() documentation Fabrizio Castro
2019-08-28 11:21 ` [cip-dev] [PATCH/RFC 4.19.y-cip 13/41] pinctrl: sh-pfc: Rename 2-parameter CPU_ALL_PORT() variant Fabrizio Castro
2019-08-28 11:21 ` [cip-dev] [PATCH/RFC 4.19.y-cip 14/41] pinctrl: sh-pfc: Add SH_PFC_PIN_CFG_PULL_UP_DOWN shorthand Fabrizio Castro
2019-08-28 11:21 ` [cip-dev] [PATCH/RFC 4.19.y-cip 15/41] pinctrl: sh-pfc: Add new non-GPIO helper macros Fabrizio Castro
2019-08-28 11:21 ` [cip-dev] [PATCH/RFC 4.19.y-cip 16/41] pinctrl: sh-pfc: Correct printk level of group reference warning Fabrizio Castro
2019-08-28 11:21 ` [cip-dev] [PATCH/RFC 4.19.y-cip 17/41] pinctrl: sh-pfc: Mark run-time debug code __init Fabrizio Castro
2019-08-28 11:21 ` [cip-dev] [PATCH/RFC 4.19.y-cip 18/41] pinctrl: sh-pfc: Add check for empty pinmux groups/functions Fabrizio Castro
2019-08-28 11:21 ` [cip-dev] [PATCH/RFC 4.19.y-cip 19/41] pinctrl: sh-pfc: Validate pin tables at runtime Fabrizio Castro
2019-08-28 11:21 ` [cip-dev] [PATCH/RFC 4.19.y-cip 20/41] pinctrl: sh-pfc: r8a7796: Fix VIN versioned groups Fabrizio Castro
2019-08-28 11:21 ` Fabrizio Castro [this message]
2019-08-28 11:21 ` [cip-dev] [PATCH/RFC 4.19.y-cip 22/41] pinctrl: sh-pfc: r8a7796: Deduplicate VIN5 pin definitions Fabrizio Castro
2019-08-28 11:21 ` [cip-dev] [PATCH/RFC 4.19.y-cip 23/41] pinctrl: sh-pfc: r8a7796: Move CANFD pin groups and functions Fabrizio Castro
2019-08-28 11:21 ` [cip-dev] [PATCH/RFC 4.19.y-cip 24/41] pinctrl: sh-pfc: r8a77990: Rename IOCTRLx registers Fabrizio Castro
2019-08-28 11:21 ` [cip-dev] [PATCH/RFC 4.19.y-cip 25/41] pinctrl: sh-pfc: r8a77990: Move CANFD pin groups and functions Fabrizio Castro
2019-08-28 11:21 ` [cip-dev] [PATCH/RFC 4.19.y-cip 26/41] pinctrl: sh-pfc: rcar-gen3: Retain TDSELCTRL register across suspend/resume Fabrizio Castro
2019-08-28 11:21 ` [cip-dev] [PATCH/RFC 4.19.y-cip 27/41] pinctrl: sh-pfc: Add missing #include <linux/errno.h> Fabrizio Castro
2019-08-28 11:21 ` [cip-dev] [PATCH/RFC 4.19.y-cip 28/41] pinctrl: sh-pfc: rcar-gen3: Remove HDMI CEC pins, groups, and functions Fabrizio Castro
2019-08-28 11:21 ` [cip-dev] [PATCH/RFC 4.19.y-cip 29/41] pinctrl: sh-pfc: rcar-gen3: Remove CC5_OSCOUT pin Fabrizio Castro
2019-08-28 11:21 ` [cip-dev] [PATCH/RFC 4.19.y-cip 30/41] pinctrl: sh-pfc: rcar-gen3: Rename SEL_ADG_{A, B, C} to SEL_ADG{A, B, C} Fabrizio Castro
2019-08-28 11:21 ` [cip-dev] [PATCH/RFC 4.19.y-cip 31/41] pinctrl: sh-pfc: r8a77990: Fix MOD_SEL0 bit16 when using NFALE and NFRB_N Fabrizio Castro
2019-08-28 11:21 ` [cip-dev] [PATCH/RFC 4.19.y-cip 32/41] pinctrl: sh-pfc: r8a77990: Fix MOD_SEL1 bit31 when using SIM0_D Fabrizio Castro
2019-08-28 11:22 ` [cip-dev] [PATCH/RFC 4.19.y-cip 33/41] pinctrl: sh-pfc: r8a77990: Fix MOD_SEL1 bit30 when using SSI_SCK2 and SSI_WS2 Fabrizio Castro
2019-08-28 11:22 ` [cip-dev] [PATCH/RFC 4.19.y-cip 34/41] pinctrl: sh-pfc: rcar-gen3: Rename RTS{0, 1, 3, 4}# pin function definitions Fabrizio Castro
2019-08-28 11:22 ` [cip-dev] [PATCH/RFC 4.19.y-cip 35/41] pinctrl: sh-pfc: rcar-gen3: Rename SEL_NDFC to SEL_NDF Fabrizio Castro
2019-08-28 11:22 ` [cip-dev] [PATCH/RFC 4.19.y-cip 36/41] pinctrl: sh-pfc: Add PORT_GP_27 helper macro Fabrizio Castro
2019-08-28 11:22 ` [cip-dev] [PATCH/RFC 4.19.y-cip 37/41] pinctrl: sh-pfc: Move PIN_NONE to shared header file Fabrizio Castro
2019-08-28 11:22 ` [cip-dev] [PATCH/RFC 4.19.y-cip 38/41] pinctrl: sh-pfc: r8a77990: Use new macros for non-GPIO pins Fabrizio Castro
2019-08-28 11:22 ` [cip-dev] [PATCH/RFC 4.19.y-cip 39/41] pinctrl: sh-pfc: r8a7796: Add TPU pins, groups and functions Fabrizio Castro
2019-08-28 11:22 ` [cip-dev] [PATCH/RFC 4.19.y-cip 40/41] pinctrl: sh-pfc: r8a7796: Use new macros for non-GPIO pins Fabrizio Castro
2019-08-28 11:22 ` [cip-dev] [PATCH/RFC 4.19.y-cip 41/41] pinctrl: sh-pfc: r8a7796: Remove placeholder I2C pin data Fabrizio Castro
2019-08-29 8:12 ` [cip-dev] [PATCH/RFC 4.19.y-cip 00/41] Fast forward sh-pfc Pavel Machek
2019-08-29 9:36 ` Fabrizio Castro
2019-08-29 9:47 ` Pavel Machek
2019-08-29 9:49 ` Fabrizio Castro
2019-08-29 10:23 ` Chris Paterson
2019-08-29 11:04 ` Fabrizio Castro
2019-08-29 13:51 ` Ben Hutchings
2019-08-29 17:07 ` Fabrizio Castro
2019-08-29 20:04 ` Pavel Machek
2019-08-29 22:35 ` Pavel Machek
2019-08-30 7:26 ` Chris Paterson
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