From: Sivaprakash Murugesan <sivaprak@codeaurora.org>
To: agross@kernel.org, bjorn.andersson@linaro.org,
bhelgaas@google.com, robh+dt@kernel.org, kishon@ti.com,
vkoul@kernel.org, mturquette@baylibre.com, sboyd@kernel.org,
svarbanov@mm-sol.com, lorenzo.pieralisi@arm.com,
p.zabel@pengutronix.de, sivaprak@codeaurora.org,
mgautam@codeaurora.org, smuthayy@codeaurora.org,
varada@codeaurora.org, linux-arm-msm@vger.kernel.org,
linux-pci@vger.kernel.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org
Cc: Selvam Sathappan Periakaruppan <speriaka@codeaurora.org>
Subject: [PATCH 4/9] clk: qcom: ipq8074: Add missing clocks for pcie
Date: Sun, 5 Jul 2020 14:47:55 +0530 [thread overview]
Message-ID: <1593940680-2363-5-git-send-email-sivaprak@codeaurora.org> (raw)
In-Reply-To: <1593940680-2363-1-git-send-email-sivaprak@codeaurora.org>
Add missing clocks and resets for pcie port0 of ipq8074 devices.
Co-developed-by: Selvam Sathappan Periakaruppan <speriaka@codeaurora.org>
Signed-off-by: Selvam Sathappan Periakaruppan <speriaka@codeaurora.org>
Signed-off-by: Sivaprakash Murugesan <sivaprak@codeaurora.org>
---
drivers/clk/qcom/gcc-ipq8074.c | 60 ++++++++++++++++++++++++++++++++++++++++++
1 file changed, 60 insertions(+)
diff --git a/drivers/clk/qcom/gcc-ipq8074.c b/drivers/clk/qcom/gcc-ipq8074.c
index e01f5f591d1e..443e28cda8ed 100644
--- a/drivers/clk/qcom/gcc-ipq8074.c
+++ b/drivers/clk/qcom/gcc-ipq8074.c
@@ -4316,6 +4316,62 @@ static struct clk_branch gcc_gp3_clk = {
},
};
+struct freq_tbl ftbl_pcie_rchng_clk_src[] = {
+ F(19200000, P_XO, 1, 0, 0),
+ F(100000000, P_GPLL0, 8, 0, 0),
+ { }
+};
+
+struct clk_rcg2 pcie0_rchng_clk_src = {
+ .cmd_rcgr = 0x75070,
+ .freq_tbl = ftbl_pcie_rchng_clk_src,
+ .hid_width = 5,
+ .parent_map = gcc_xo_gpll0_map,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "pcie0_rchng_clk_src",
+ .parent_hws = (const struct clk_hw *[]) {
+ &gpll0.clkr.hw },
+ .num_parents = 2,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_branch gcc_pcie0_rchng_clk = {
+ .halt_reg = 0x75070,
+ .halt_bit = 31,
+ .clkr = {
+ .enable_reg = 0x75070,
+ .enable_mask = BIT(1),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_pcie0_rchng_clk",
+ .parent_hws = (const struct clk_hw *[]){
+ &pcie0_rchng_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_pcie0_axi_s_bridge_clk = {
+ .halt_reg = 0x75048,
+ .halt_bit = 31,
+ .clkr = {
+ .enable_reg = 0x75048,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_pcie0_axi_s_bridge_clk",
+ .parent_hws = (const struct clk_hw *[]){
+ &pcie0_axi_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
static struct clk_hw *gcc_ipq8074_hws[] = {
&gpll0_out_main_div2.hw,
&gpll6_out_main_div2.hw,
@@ -4551,6 +4607,9 @@ static struct clk_regmap *gcc_ipq8074_clks[] = {
[GCC_GP1_CLK] = &gcc_gp1_clk.clkr,
[GCC_GP2_CLK] = &gcc_gp2_clk.clkr,
[GCC_GP3_CLK] = &gcc_gp3_clk.clkr,
+ [GCC_PCIE0_RCHNG_CLK_SRC] = &pcie0_rchng_clk_src.clkr,
+ [GCC_PCIE0_RCHNG_CLK] = &gcc_pcie0_rchng_clk.clkr,
+ [GCC_PCIE0_AXI_S_BRIDGE_CLK] = &gcc_pcie0_axi_s_bridge_clk.clkr,
};
static const struct qcom_reset_map gcc_ipq8074_resets[] = {
@@ -4678,6 +4737,7 @@ static const struct qcom_reset_map gcc_ipq8074_resets[] = {
[GCC_PCIE0_AXI_SLAVE_ARES] = { 0x75040, 4 },
[GCC_PCIE0_AHB_ARES] = { 0x75040, 5 },
[GCC_PCIE0_AXI_MASTER_STICKY_ARES] = { 0x75040, 6 },
+ [GCC_PCIE0_AXI_SLAVE_STICKY_ARES] = { 0x75040, 7 },
[GCC_PCIE1_PIPE_ARES] = { 0x76040, 0 },
[GCC_PCIE1_SLEEP_ARES] = { 0x76040, 1 },
[GCC_PCIE1_CORE_STICKY_ARES] = { 0x76040, 2 },
--
2.7.4
next prev parent reply other threads:[~2020-07-05 9:18 UTC|newest]
Thread overview: 22+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-07-05 9:17 [PATCH 0/9] Add PCIe support for IPQ8074 Sivaprakash Murugesan
2020-07-05 9:17 ` [PATCH 1/9] dt-bindings: pci: Add ipq8074 gen3 pci compatible Sivaprakash Murugesan
2020-07-15 21:50 ` Rob Herring
2020-07-05 9:17 ` [PATCH 2/9] dt-bindings: phy: qcom,qmp: Add dt-binding for ipq8074 gen3 pcie phy Sivaprakash Murugesan
2020-07-15 21:50 ` Rob Herring
2020-07-05 9:17 ` [PATCH 3/9] clk: qcom: ipq8074: Add missing bindings for pcie Sivaprakash Murugesan
2020-07-11 16:12 ` Stephen Boyd
2020-07-05 9:17 ` Sivaprakash Murugesan [this message]
2020-07-11 16:10 ` [PATCH 4/9] clk: qcom: ipq8074: Add missing clocks " Stephen Boyd
2020-07-11 16:12 ` Stephen Boyd
2020-07-05 9:17 ` [PATCH 5/9] phy: qcom-qmp: use correct values for ipq8074 gen2 pcie phy init Sivaprakash Murugesan
2020-07-10 14:02 ` Sasha Levin
2020-07-13 5:55 ` Vinod Koul
2020-07-29 6:45 ` Sivaprakash Murugesan
2020-08-03 11:03 ` Vinod Koul
2020-07-05 9:17 ` [PATCH 6/9] phy: qcom-qmp: Add compatible for ipq8074 pcie gen3 qmp phy Sivaprakash Murugesan
2020-07-13 6:04 ` Vinod Koul
2020-07-29 7:46 ` Sivaprakash Murugesan
2020-07-05 9:17 ` [PATCH 7/9] pci: dwc: qcom: do phy power on before pcie init Sivaprakash Murugesan
2020-07-05 9:17 ` [PATCH 8/9] pci: qcom: Add support for ipq8074 pci controller Sivaprakash Murugesan
2020-07-05 9:18 ` [PATCH 9/9] arm64: dts: ipq8074: Fixup pcie dts nodes Sivaprakash Murugesan
2020-07-06 23:49 ` [PATCH 0/9] Add PCIe support for IPQ8074 Bjorn Helgaas
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