From: Michael Ellerman <patch-notifications@ellerman.id.au>
To: mpe@ellerman.id.au, Athira Rajeev <atrajeev@linux.vnet.ibm.com>
Cc: maddy@linux.vnet.ibm.com, linuxppc-dev@lists.ozlabs.org
Subject: Re: [PATCH] powerpc/perf: Fix reading of MSR[HV PR] bits in trace-imc
Date: Thu, 27 Aug 2020 17:46:49 +1000 (AEST) [thread overview]
Message-ID: <159851436161.52163.1873318093208618820.b4-ty@ellerman.id.au> (raw)
In-Reply-To: <1598424029-1662-1-git-send-email-atrajeev@linux.vnet.ibm.com>
On Wed, 26 Aug 2020 02:40:29 -0400, Athira Rajeev wrote:
> IMC trace-mode uses MSR[HV PR] bits to set the cpumode
> for the instruction pointer captured in each sample.
> The bits are fetched from third DW of the trace record.
> Reading third DW from IMC trace record should use be64_to_cpu
> along with READ_ONCE inorder to fetch correct MSR[HV PR] bits.
> Patch addresses this change.
>
> [...]
Applied to powerpc/fixes.
[1/1] powerpc/perf: Fix reading of MSR[HV/PR] bits in trace-imc
https://git.kernel.org/powerpc/c/82715a0f332843d3a1830d7ebc9ac7c99a00c880
cheers
prev parent reply other threads:[~2020-08-27 7:49 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-08-26 6:40 [PATCH] powerpc/perf: Fix reading of MSR[HV PR] bits in trace-imc Athira Rajeev
2020-08-27 7:46 ` Michael Ellerman [this message]
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