From: "tip-bot2 for Thomas Gleixner" <tip-bot2@linutronix.de>
To: linux-tip-commits@vger.kernel.org
Cc: Thomas Gleixner <tglx@linutronix.de>,
David Woodhouse <dwmw@amazon.co.uk>, x86 <x86@kernel.org>,
LKML <linux-kernel@vger.kernel.org>
Subject: [tip: x86/apic] x86/apic: Cleanup delivery mode defines
Date: Thu, 29 Oct 2020 12:15:46 -0000 [thread overview]
Message-ID: <160397374697.397.2430389140744938107.tip-bot2@tip-bot2> (raw)
In-Reply-To: <20201024213535.443185-6-dwmw2@infradead.org>
The following commit has been merged into the x86/apic branch of tip:
Commit-ID: 721612994f53ed600b39a80d912b10f51960e2e3
Gitweb: https://git.kernel.org/tip/721612994f53ed600b39a80d912b10f51960e2e3
Author: Thomas Gleixner <tglx@linutronix.de>
AuthorDate: Sat, 24 Oct 2020 22:35:05 +01:00
Committer: Thomas Gleixner <tglx@linutronix.de>
CommitterDate: Wed, 28 Oct 2020 20:26:24 +01:00
x86/apic: Cleanup delivery mode defines
The enum ioapic_irq_destination_types and the enumerated constants starting
with 'dest_' are gross misnomers because they describe the delivery mode.
Rename then enum and the constants so they actually make sense.
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: David Woodhouse <dwmw@amazon.co.uk>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Link: https://lore.kernel.org/r/20201024213535.443185-6-dwmw2@infradead.org
---
arch/x86/include/asm/apic.h | 3 ++-
arch/x86/include/asm/apicdef.h | 16 +++++++---------
arch/x86/kernel/apic/apic_flat_64.c | 4 ++--
arch/x86/kernel/apic/apic_noop.c | 2 +-
arch/x86/kernel/apic/apic_numachip.c | 4 ++--
arch/x86/kernel/apic/bigsmp_32.c | 2 +-
arch/x86/kernel/apic/io_apic.c | 11 ++++++-----
arch/x86/kernel/apic/probe_32.c | 2 +-
arch/x86/kernel/apic/x2apic_cluster.c | 2 +-
arch/x86/kernel/apic/x2apic_phys.c | 2 +-
arch/x86/kernel/apic/x2apic_uv_x.c | 6 +++---
arch/x86/platform/uv/uv_irq.c | 2 +-
drivers/iommu/amd/iommu.c | 4 ++--
drivers/iommu/intel/irq_remapping.c | 2 +-
drivers/pci/controller/pci-hyperv.c | 6 +++---
15 files changed, 34 insertions(+), 34 deletions(-)
diff --git a/arch/x86/include/asm/apic.h b/arch/x86/include/asm/apic.h
index 57af25c..37a08f3 100644
--- a/arch/x86/include/asm/apic.h
+++ b/arch/x86/include/asm/apic.h
@@ -309,7 +309,8 @@ struct apic {
/* dest_logical is used by the IPI functions */
u32 dest_logical;
u32 disable_esr;
- u32 irq_delivery_mode;
+
+ enum apic_delivery_modes delivery_mode;
u32 irq_dest_mode;
u32 (*calc_dest_apicid)(unsigned int cpu);
diff --git a/arch/x86/include/asm/apicdef.h b/arch/x86/include/asm/apicdef.h
index 05e694e..5716f22 100644
--- a/arch/x86/include/asm/apicdef.h
+++ b/arch/x86/include/asm/apicdef.h
@@ -432,15 +432,13 @@ struct local_apic {
#define BAD_APICID 0xFFFFu
#endif
-enum ioapic_irq_destination_types {
- dest_Fixed = 0,
- dest_LowestPrio = 1,
- dest_SMI = 2,
- dest__reserved_1 = 3,
- dest_NMI = 4,
- dest_INIT = 5,
- dest__reserved_2 = 6,
- dest_ExtINT = 7
+enum apic_delivery_modes {
+ APIC_DELIVERY_MODE_FIXED = 0,
+ APIC_DELIVERY_MODE_LOWESTPRIO = 1,
+ APIC_DELIVERY_MODE_SMI = 2,
+ APIC_DELIVERY_MODE_NMI = 4,
+ APIC_DELIVERY_MODE_INIT = 5,
+ APIC_DELIVERY_MODE_EXTINT = 7,
};
#endif /* _ASM_X86_APICDEF_H */
diff --git a/arch/x86/kernel/apic/apic_flat_64.c b/arch/x86/kernel/apic/apic_flat_64.c
index 7862b15..fdd38a1 100644
--- a/arch/x86/kernel/apic/apic_flat_64.c
+++ b/arch/x86/kernel/apic/apic_flat_64.c
@@ -113,7 +113,7 @@ static struct apic apic_flat __ro_after_init = {
.apic_id_valid = default_apic_id_valid,
.apic_id_registered = flat_apic_id_registered,
- .irq_delivery_mode = dest_Fixed,
+ .delivery_mode = APIC_DELIVERY_MODE_FIXED,
.irq_dest_mode = 1, /* logical */
.disable_esr = 0,
@@ -206,7 +206,7 @@ static struct apic apic_physflat __ro_after_init = {
.apic_id_valid = default_apic_id_valid,
.apic_id_registered = flat_apic_id_registered,
- .irq_delivery_mode = dest_Fixed,
+ .delivery_mode = APIC_DELIVERY_MODE_FIXED,
.irq_dest_mode = 0, /* physical */
.disable_esr = 0,
diff --git a/arch/x86/kernel/apic/apic_noop.c b/arch/x86/kernel/apic/apic_noop.c
index 780c702..4fc934b 100644
--- a/arch/x86/kernel/apic/apic_noop.c
+++ b/arch/x86/kernel/apic/apic_noop.c
@@ -95,7 +95,7 @@ struct apic apic_noop __ro_after_init = {
.apic_id_valid = default_apic_id_valid,
.apic_id_registered = noop_apic_id_registered,
- .irq_delivery_mode = dest_Fixed,
+ .delivery_mode = APIC_DELIVERY_MODE_FIXED,
/* logical delivery broadcast to all CPUs: */
.irq_dest_mode = 1,
diff --git a/arch/x86/kernel/apic/apic_numachip.c b/arch/x86/kernel/apic/apic_numachip.c
index 35edd57..db715d0 100644
--- a/arch/x86/kernel/apic/apic_numachip.c
+++ b/arch/x86/kernel/apic/apic_numachip.c
@@ -246,7 +246,7 @@ static const struct apic apic_numachip1 __refconst = {
.apic_id_valid = numachip_apic_id_valid,
.apic_id_registered = numachip_apic_id_registered,
- .irq_delivery_mode = dest_Fixed,
+ .delivery_mode = APIC_DELIVERY_MODE_FIXED,
.irq_dest_mode = 0, /* physical */
.disable_esr = 0,
@@ -295,7 +295,7 @@ static const struct apic apic_numachip2 __refconst = {
.apic_id_valid = numachip_apic_id_valid,
.apic_id_registered = numachip_apic_id_registered,
- .irq_delivery_mode = dest_Fixed,
+ .delivery_mode = APIC_DELIVERY_MODE_FIXED,
.irq_dest_mode = 0, /* physical */
.disable_esr = 0,
diff --git a/arch/x86/kernel/apic/bigsmp_32.c b/arch/x86/kernel/apic/bigsmp_32.c
index 98d015a..7f6461f 100644
--- a/arch/x86/kernel/apic/bigsmp_32.c
+++ b/arch/x86/kernel/apic/bigsmp_32.c
@@ -127,7 +127,7 @@ static struct apic apic_bigsmp __ro_after_init = {
.apic_id_valid = default_apic_id_valid,
.apic_id_registered = bigsmp_apic_id_registered,
- .irq_delivery_mode = dest_Fixed,
+ .delivery_mode = APIC_DELIVERY_MODE_FIXED,
/* phys delivery to target CPU: */
.irq_dest_mode = 0,
diff --git a/arch/x86/kernel/apic/io_apic.c b/arch/x86/kernel/apic/io_apic.c
index 7b3c7e0..cff6cbc 100644
--- a/arch/x86/kernel/apic/io_apic.c
+++ b/arch/x86/kernel/apic/io_apic.c
@@ -535,7 +535,7 @@ static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin)
/* Check delivery_mode to be sure we're not clearing an SMI pin */
entry = ioapic_read_entry(apic, pin);
- if (entry.delivery_mode == dest_SMI)
+ if (entry.delivery_mode == APIC_DELIVERY_MODE_SMI)
return;
/*
@@ -1368,7 +1368,8 @@ void __init enable_IO_APIC(void)
/* If the interrupt line is enabled and in ExtInt mode
* I have found the pin where the i8259 is connected.
*/
- if ((entry.mask == 0) && (entry.delivery_mode == dest_ExtINT)) {
+ if ((entry.mask == 0) &&
+ (entry.delivery_mode == APIC_DELIVERY_MODE_EXTINT)) {
ioapic_i8259.apic = apic;
ioapic_i8259.pin = pin;
goto found_i8259;
@@ -1416,7 +1417,7 @@ void native_restore_boot_irq_mode(void)
entry.trigger = IOAPIC_EDGE;
entry.polarity = IOAPIC_POL_HIGH;
entry.dest_mode = IOAPIC_DEST_MODE_PHYSICAL;
- entry.delivery_mode = dest_ExtINT;
+ entry.delivery_mode = APIC_DELIVERY_MODE_EXTINT;
entry.dest = read_apic_id();
/*
@@ -2047,7 +2048,7 @@ static inline void __init unlock_ExtINT_logic(void)
entry1.dest_mode = IOAPIC_DEST_MODE_PHYSICAL;
entry1.mask = IOAPIC_UNMASKED;
entry1.dest = hard_smp_processor_id();
- entry1.delivery_mode = dest_ExtINT;
+ entry1.delivery_mode = APIC_DELIVERY_MODE_EXTINT;
entry1.polarity = entry0.polarity;
entry1.trigger = IOAPIC_EDGE;
entry1.vector = 0;
@@ -2948,7 +2949,7 @@ static void mp_setup_entry(struct irq_cfg *cfg, struct mp_chip_data *data,
struct IO_APIC_route_entry *entry)
{
memset(entry, 0, sizeof(*entry));
- entry->delivery_mode = apic->irq_delivery_mode;
+ entry->delivery_mode = apic->delivery_mode;
entry->dest_mode = apic->irq_dest_mode;
entry->dest = cfg->dest_apicid;
entry->vector = cfg->vector;
diff --git a/arch/x86/kernel/apic/probe_32.c b/arch/x86/kernel/apic/probe_32.c
index 67b6f7c..77c6e2e 100644
--- a/arch/x86/kernel/apic/probe_32.c
+++ b/arch/x86/kernel/apic/probe_32.c
@@ -69,7 +69,7 @@ static struct apic apic_default __ro_after_init = {
.apic_id_valid = default_apic_id_valid,
.apic_id_registered = default_apic_id_registered,
- .irq_delivery_mode = dest_Fixed,
+ .delivery_mode = APIC_DELIVERY_MODE_FIXED,
/* logical delivery broadcast to all CPUs: */
.irq_dest_mode = 1,
diff --git a/arch/x86/kernel/apic/x2apic_cluster.c b/arch/x86/kernel/apic/x2apic_cluster.c
index b0889c4..82fb43d 100644
--- a/arch/x86/kernel/apic/x2apic_cluster.c
+++ b/arch/x86/kernel/apic/x2apic_cluster.c
@@ -184,7 +184,7 @@ static struct apic apic_x2apic_cluster __ro_after_init = {
.apic_id_valid = x2apic_apic_id_valid,
.apic_id_registered = x2apic_apic_id_registered,
- .irq_delivery_mode = dest_Fixed,
+ .delivery_mode = APIC_DELIVERY_MODE_FIXED,
.irq_dest_mode = 1, /* logical */
.disable_esr = 0,
diff --git a/arch/x86/kernel/apic/x2apic_phys.c b/arch/x86/kernel/apic/x2apic_phys.c
index e14eae6..437e843 100644
--- a/arch/x86/kernel/apic/x2apic_phys.c
+++ b/arch/x86/kernel/apic/x2apic_phys.c
@@ -157,7 +157,7 @@ static struct apic apic_x2apic_phys __ro_after_init = {
.apic_id_valid = x2apic_apic_id_valid,
.apic_id_registered = x2apic_apic_id_registered,
- .irq_delivery_mode = dest_Fixed,
+ .delivery_mode = APIC_DELIVERY_MODE_FIXED,
.irq_dest_mode = 0, /* physical */
.disable_esr = 0,
diff --git a/arch/x86/kernel/apic/x2apic_uv_x.c b/arch/x86/kernel/apic/x2apic_uv_x.c
index 9ade9e6..49deefd 100644
--- a/arch/x86/kernel/apic/x2apic_uv_x.c
+++ b/arch/x86/kernel/apic/x2apic_uv_x.c
@@ -703,9 +703,9 @@ static void uv_send_IPI_one(int cpu, int vector)
unsigned long dmode, val;
if (vector == NMI_VECTOR)
- dmode = dest_NMI;
+ dmode = APIC_DELIVERY_MODE_NMI;
else
- dmode = dest_Fixed;
+ dmode = APIC_DELIVERY_MODE_FIXED;
val = (1UL << UVH_IPI_INT_SEND_SHFT) |
(apicid << UVH_IPI_INT_APIC_ID_SHFT) |
@@ -807,7 +807,7 @@ static struct apic apic_x2apic_uv_x __ro_after_init = {
.apic_id_valid = uv_apic_id_valid,
.apic_id_registered = uv_apic_id_registered,
- .irq_delivery_mode = dest_Fixed,
+ .delivery_mode = APIC_DELIVERY_MODE_FIXED,
.irq_dest_mode = 0, /* Physical */
.disable_esr = 0,
diff --git a/arch/x86/platform/uv/uv_irq.c b/arch/x86/platform/uv/uv_irq.c
index 18ca226..e7020d1 100644
--- a/arch/x86/platform/uv/uv_irq.c
+++ b/arch/x86/platform/uv/uv_irq.c
@@ -35,7 +35,7 @@ static void uv_program_mmr(struct irq_cfg *cfg, struct uv_irq_2_mmr_pnode *info)
mmr_value = 0;
entry = (struct uv_IO_APIC_route_entry *)&mmr_value;
entry->vector = cfg->vector;
- entry->delivery_mode = apic->irq_delivery_mode;
+ entry->delivery_mode = apic->delivery_mode;
entry->dest_mode = apic->irq_dest_mode;
entry->polarity = 0;
entry->trigger = 0;
diff --git a/drivers/iommu/amd/iommu.c b/drivers/iommu/amd/iommu.c
index b9cf594..bc81b91 100644
--- a/drivers/iommu/amd/iommu.c
+++ b/drivers/iommu/amd/iommu.c
@@ -3671,7 +3671,7 @@ static void irq_remapping_prepare_irte(struct amd_ir_data *data,
data->irq_2_irte.devid = devid;
data->irq_2_irte.index = index + sub_handle;
- iommu->irte_ops->prepare(data->entry, apic->irq_delivery_mode,
+ iommu->irte_ops->prepare(data->entry, apic->delivery_mode,
apic->irq_dest_mode, irq_cfg->vector,
irq_cfg->dest_apicid, devid);
@@ -3944,7 +3944,7 @@ int amd_iommu_deactivate_guest_mode(void *data)
entry->lo.fields_remap.valid = valid;
entry->lo.fields_remap.dm = apic->irq_dest_mode;
- entry->lo.fields_remap.int_type = apic->irq_delivery_mode;
+ entry->lo.fields_remap.int_type = apic->delivery_mode;
entry->hi.fields.vector = cfg->vector;
entry->lo.fields_remap.destination =
APICID_TO_IRTE_DEST_LO(cfg->dest_apicid);
diff --git a/drivers/iommu/intel/irq_remapping.c b/drivers/iommu/intel/irq_remapping.c
index 0cfce1d..d44e719 100644
--- a/drivers/iommu/intel/irq_remapping.c
+++ b/drivers/iommu/intel/irq_remapping.c
@@ -1122,7 +1122,7 @@ static void prepare_irte(struct irte *irte, int vector, unsigned int dest)
* irq migration in the presence of interrupt-remapping.
*/
irte->trigger_mode = 0;
- irte->dlvry_mode = apic->irq_delivery_mode;
+ irte->dlvry_mode = apic->delivery_mode;
irte->vector = vector;
irte->dest_id = IRTE_DEST(dest);
irte->redir_hint = 1;
diff --git a/drivers/pci/controller/pci-hyperv.c b/drivers/pci/controller/pci-hyperv.c
index 03ed5cb..6db8d96 100644
--- a/drivers/pci/controller/pci-hyperv.c
+++ b/drivers/pci/controller/pci-hyperv.c
@@ -1226,7 +1226,7 @@ static void hv_irq_unmask(struct irq_data *data)
params->int_target.vector = cfg->vector;
/*
- * Honoring apic->irq_delivery_mode set to dest_Fixed by
+ * Honoring apic->delivery_mode set to APIC_DELIVERY_MODE_FIXED by
* setting the HV_DEVICE_INTERRUPT_TARGET_MULTICAST flag results in a
* spurious interrupt storm. Not doing so does not seem to have a
* negative effect (yet?).
@@ -1324,7 +1324,7 @@ static u32 hv_compose_msi_req_v1(
int_pkt->wslot.slot = slot;
int_pkt->int_desc.vector = vector;
int_pkt->int_desc.vector_count = 1;
- int_pkt->int_desc.delivery_mode = dest_Fixed;
+ int_pkt->int_desc.delivery_mode = APIC_DELIVERY_MODE_FIXED;
/*
* Create MSI w/ dummy vCPU set, overwritten by subsequent retarget in
@@ -1345,7 +1345,7 @@ static u32 hv_compose_msi_req_v2(
int_pkt->wslot.slot = slot;
int_pkt->int_desc.vector = vector;
int_pkt->int_desc.vector_count = 1;
- int_pkt->int_desc.delivery_mode = dest_Fixed;
+ int_pkt->int_desc.delivery_mode = APIC_DELIVERY_MODE_FIXED;
/*
* Create MSI w/ dummy vCPU set targeting just one vCPU, overwritten
next prev parent reply other threads:[~2020-10-29 12:16 UTC|newest]
Thread overview: 254+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-10-07 12:20 [PATCH 0/5] Fix x2apic enablement and allow up to 32768 CPUs without IR where supported David Woodhouse
2020-10-07 12:20 ` [PATCH 1/5] x86/apic: Fix x2apic enablement without interrupt remapping David Woodhouse
2020-10-07 12:20 ` [PATCH 2/5] x86/msi: Only use high bits of MSI address for DMAR unit David Woodhouse
2020-10-07 12:20 ` [PATCH 3/5] x86/ioapic: Handle Extended Destination ID field in RTE David Woodhouse
2020-10-08 9:12 ` Peter Zijlstra
2020-10-08 17:05 ` David Woodhouse
2020-10-08 11:41 ` Thomas Gleixner
2020-10-07 12:20 ` [PATCH 4/5] x86/apic: Support 15 bits of APIC ID in IOAPIC/MSI where available David Woodhouse
2020-10-08 11:54 ` Thomas Gleixner
2020-10-08 12:02 ` Thomas Gleixner
2020-10-08 13:00 ` David Woodhouse
2020-10-07 12:20 ` [PATCH 5/5] x86/kvm: Add KVM_FEATURE_MSI_EXT_DEST_ID David Woodhouse
2020-10-08 12:05 ` Thomas Gleixner
2020-10-08 12:55 ` David Woodhouse
2020-10-08 16:08 ` David Woodhouse
2020-10-08 21:14 ` Thomas Gleixner
2020-10-08 21:39 ` David Woodhouse
2020-10-08 23:27 ` Thomas Gleixner
2020-10-09 6:07 ` David Woodhouse
2020-10-10 10:06 ` David Woodhouse
2020-10-10 11:44 ` Thomas Gleixner
2020-10-10 11:58 ` David Woodhouse
2020-10-11 17:12 ` Thomas Gleixner
2020-10-11 21:15 ` David Woodhouse
2020-10-12 9:33 ` Thomas Gleixner
2020-10-12 16:06 ` David Woodhouse
2020-10-12 18:38 ` Thomas Gleixner
2020-10-12 20:20 ` David Woodhouse
2020-10-12 22:13 ` Thomas Gleixner
2020-10-13 7:52 ` David Woodhouse
2020-10-13 8:11 ` [PATCH 0/9] Remove irq_remapping_get_irq_domain() David Woodhouse
2020-10-13 8:11 ` David Woodhouse
2020-10-13 8:11 ` [PATCH 1/9] genirq/irqdomain: Implement get_name() method on irqchip fwnodes David Woodhouse
2020-10-13 8:11 ` David Woodhouse
2020-10-13 8:11 ` [PATCH 2/9] x86/apic: Add select() method on vector irqdomain David Woodhouse
2020-10-13 8:11 ` David Woodhouse
2020-10-13 8:11 ` [PATCH 3/9] iommu/amd: Implement select() method on remapping irqdomain David Woodhouse
2020-10-13 8:11 ` David Woodhouse
2020-10-13 8:11 ` [PATCH 4/9] iommu/vt-d: " David Woodhouse
2020-10-13 8:11 ` David Woodhouse
2020-10-13 8:11 ` [PATCH 5/9] iommu/hyper-v: " David Woodhouse
2020-10-13 8:11 ` David Woodhouse
2020-10-13 8:11 ` [PATCH 6/9] x86/hpet: Use irq_find_matching_fwspec() to find " David Woodhouse
2020-10-13 8:11 ` David Woodhouse
2020-10-13 8:11 ` [PATCH 7/9] x86/ioapic: " David Woodhouse
2020-10-13 8:11 ` David Woodhouse
2020-10-13 8:11 ` [PATCH 8/9] x86: Kill all traces of irq_remapping_get_irq_domain() David Woodhouse
2020-10-13 8:11 ` David Woodhouse
2020-10-13 8:11 ` [PATCH 9/9] iommu/vt-d: Simplify intel_irq_remapping_select() David Woodhouse
2020-10-13 8:11 ` David Woodhouse
2020-10-13 9:28 ` [PATCH 5/5] x86/kvm: Add KVM_FEATURE_MSI_EXT_DEST_ID Thomas Gleixner
2020-10-13 10:15 ` David Woodhouse
2020-10-13 10:46 ` Thomas Gleixner
2020-10-13 10:53 ` David Woodhouse
2020-10-13 11:51 ` David Woodhouse
2020-10-13 12:40 ` Thomas Gleixner
2020-10-08 11:46 ` [PATCH 1/5] x86/apic: Fix x2apic enablement without interrupt remapping Thomas Gleixner
2020-10-09 10:46 ` [PATCH v2 0/8] Fix x2apic enablement and allow up to 32768 CPUs without IR where supported David Woodhouse
2020-10-09 10:46 ` [PATCH v2 1/8] x86/apic: Fix x2apic enablement without interrupt remapping David Woodhouse
2020-10-09 10:46 ` [PATCH v2 2/8] x86/msi: Only use high bits of MSI address for DMAR unit David Woodhouse
2020-10-09 10:46 ` [PATCH v2 3/8] x86/apic: Always provide irq_compose_msi_msg() method for vector domain David Woodhouse
2020-10-09 10:46 ` [PATCH v2 4/8] x86/ioapic: Handle Extended Destination ID field in RTE David Woodhouse
2020-10-09 10:46 ` [PATCH v2 5/8] x86/apic: Support 15 bits of APIC ID in MSI where available David Woodhouse
2020-10-09 10:46 ` [PATCH v2 6/8] x86/kvm: Add KVM_FEATURE_MSI_EXT_DEST_ID David Woodhouse
2020-10-09 10:46 ` [PATCH v2 7/8] x86/hpet: Move MSI support into hpet.c David Woodhouse
2020-10-09 10:46 ` [PATCH v2 8/8] x86/ioapic: Generate RTE directly from parent irqchip's MSI message David Woodhouse
2020-10-22 21:43 ` Thomas Gleixner
2020-10-22 22:10 ` Thomas Gleixner
2020-10-23 17:04 ` David Woodhouse
2020-10-23 10:10 ` David Woodhouse
2020-10-23 21:28 ` Thomas Gleixner
2020-10-24 8:26 ` David Woodhouse
2020-10-24 8:41 ` David Woodhouse
2020-10-24 9:13 ` Paolo Bonzini
2020-10-24 10:13 ` David Woodhouse
2020-10-24 12:44 ` David Woodhouse
2020-10-24 21:35 ` [PATCH v3 00/35] Fix x2apic enablement and allow more CPUs, clean up I/OAPIC and MSI bitfields David Woodhouse
2020-10-24 21:35 ` David Woodhouse
2020-10-24 21:35 ` [PATCH v3 01/35] x86/apic: Fix x2apic enablement without interrupt remapping David Woodhouse
2020-10-24 21:35 ` David Woodhouse
2020-10-29 12:15 ` [tip: x86/apic] " tip-bot2 for David Woodhouse
2020-10-24 21:35 ` [PATCH v3 02/35] x86/msi: Only use high bits of MSI address for DMAR unit David Woodhouse
2020-10-24 21:35 ` David Woodhouse
2020-10-29 12:15 ` [tip: x86/apic] " tip-bot2 for David Woodhouse
2020-10-24 21:35 ` [PATCH v3 03/35] x86/apic/uv: Fix inconsistent destination mode David Woodhouse
2020-10-24 21:35 ` David Woodhouse
2020-10-29 12:15 ` [tip: x86/apic] " tip-bot2 for Thomas Gleixner
2020-10-24 21:35 ` [PATCH v3 04/35] x86/devicetree: Fix the ioapic interrupt type table David Woodhouse
2020-10-24 21:35 ` David Woodhouse
2020-10-29 12:15 ` [tip: x86/apic] " tip-bot2 for Thomas Gleixner
2020-10-24 21:35 ` [PATCH v3 05/35] x86/apic: Cleanup delivery mode defines David Woodhouse
2020-10-24 21:35 ` David Woodhouse
2020-10-29 12:15 ` tip-bot2 for Thomas Gleixner [this message]
2020-10-24 21:35 ` [PATCH v3 06/35] x86/apic: Replace pointless apic::dest_logical usage David Woodhouse
2020-10-24 21:35 ` David Woodhouse
2020-10-29 12:15 ` [tip: x86/apic] x86/apic: Replace pointless apic:: Dest_logical usage tip-bot2 for Thomas Gleixner
2020-10-24 21:35 ` [PATCH v3 07/35] x86/apic: Get rid of apic::dest_logical David Woodhouse
2020-10-24 21:35 ` David Woodhouse
2020-10-29 12:15 ` [tip: x86/apic] x86/apic: Get rid of apic:: Dest_logical tip-bot2 for Thomas Gleixner
2020-10-24 21:35 ` [PATCH v3 08/35] x86/apic: Cleanup destination mode David Woodhouse
2020-10-24 21:35 ` David Woodhouse
2020-10-29 12:15 ` [tip: x86/apic] " tip-bot2 for Thomas Gleixner
2020-10-24 21:35 ` [PATCH v3 09/35] x86/apic: Always provide irq_compose_msi_msg() method for vector domain David Woodhouse
2020-10-24 21:35 ` David Woodhouse
2020-10-29 12:15 ` [tip: x86/apic] " tip-bot2 for David Woodhouse
2020-10-24 21:35 ` [PATCH v3 10/35] x86/hpet: Move MSI support into hpet.c David Woodhouse
2020-10-24 21:35 ` David Woodhouse
2020-10-29 12:15 ` [tip: x86/apic] " tip-bot2 for David Woodhouse
2020-10-24 21:35 ` [PATCH v3 11/35] genirq/msi: Allow shadow declarations of msi_msg::$member David Woodhouse
2020-10-24 21:35 ` David Woodhouse
2020-10-29 12:15 ` [tip: x86/apic] genirq/msi: Allow shadow declarations of msi_msg:: $member tip-bot2 for Thomas Gleixner
2020-10-24 21:35 ` [PATCH v3 12/35] x86/msi: Provide msi message shadow structs David Woodhouse
2020-10-24 21:35 ` David Woodhouse
2020-10-29 12:15 ` [tip: x86/apic] " tip-bot2 for Thomas Gleixner
2022-04-06 8:36 ` [PATCH v3 12/35] " Reto Buerki
2022-04-06 8:36 ` Reto Buerki
2022-04-06 8:36 ` [PATCH] x86/msi: Fix msi message data shadow struct Reto Buerki
2022-04-06 8:36 ` Reto Buerki
2022-04-06 22:11 ` Thomas Gleixner
2022-04-06 22:11 ` Thomas Gleixner
2022-04-07 11:06 ` Reto Buerki
2022-04-07 11:06 ` Reto Buerki
2022-04-07 13:24 ` [tip: x86/urgent] " tip-bot2 for Reto Buerki
2022-04-06 22:07 ` [PATCH v3 12/35] x86/msi: Provide msi message shadow structs Thomas Gleixner
2022-04-06 22:07 ` Thomas Gleixner
2020-10-24 21:35 ` [PATCH v3 13/35] iommu/intel: Use msi_msg " David Woodhouse
2020-10-24 21:35 ` David Woodhouse
2020-10-29 12:15 ` [tip: x86/apic] " tip-bot2 for Thomas Gleixner
2020-10-24 21:35 ` [PATCH v3 14/35] iommu/amd: " David Woodhouse
2020-10-24 21:35 ` David Woodhouse
2020-10-29 12:15 ` [tip: x86/apic] " tip-bot2 for Thomas Gleixner
2020-10-24 21:35 ` [PATCH v3 15/35] PCI: vmd: " David Woodhouse
2020-10-24 21:35 ` David Woodhouse
2020-10-28 20:49 ` Kees Cook
2020-10-28 20:49 ` Kees Cook
2020-10-28 21:13 ` Thomas Gleixner
2020-10-28 21:13 ` Thomas Gleixner
2020-10-28 23:22 ` Kees Cook
2020-10-28 23:22 ` Kees Cook
2020-10-29 12:15 ` [tip: x86/apic] " tip-bot2 for Thomas Gleixner
2020-10-24 21:35 ` [PATCH v3 16/35] x86/kvm: " David Woodhouse
2020-10-24 21:35 ` David Woodhouse
2020-10-29 12:15 ` [tip: x86/apic] " tip-bot2 for Thomas Gleixner
2020-10-24 21:35 ` [PATCH v3 17/35] x86/pci/xen: " David Woodhouse
2020-10-24 21:35 ` David Woodhouse
2020-10-25 9:49 ` David Laight
2020-10-25 9:49 ` David Laight
2020-10-25 10:26 ` David Woodhouse
2020-10-25 10:26 ` David Woodhouse
2020-10-25 13:20 ` David Laight
2020-10-25 13:20 ` David Laight
2020-10-29 12:15 ` [tip: x86/apic] " tip-bot2 for Thomas Gleixner
2020-10-24 21:35 ` [PATCH v3 18/35] x86/msi: Remove msidef.h David Woodhouse
2020-10-24 21:35 ` David Woodhouse
2020-10-29 12:15 ` [tip: x86/apic] " tip-bot2 for Thomas Gleixner
2020-10-24 21:35 ` [PATCH v3 19/35] x86/io_apic: Cleanup trigger/polarity helpers David Woodhouse
2020-10-24 21:35 ` David Woodhouse
2020-10-29 12:15 ` [tip: x86/apic] " tip-bot2 for Thomas Gleixner
2020-11-09 23:15 ` Tom Lendacky
2020-11-10 3:30 ` [EXTERNAL] " David Woodhouse
2020-11-10 6:10 ` Borislav Petkov
2020-11-10 14:34 ` Thomas Gleixner
2020-11-10 14:55 ` Tom Lendacky
2020-11-10 15:54 ` Thomas Gleixner
2020-11-10 16:01 ` [EXTERNAL] " David Woodhouse
2020-11-10 16:17 ` Tom Lendacky
2020-11-10 16:33 ` [EXTERNAL] " David Woodhouse
2020-11-10 17:04 ` Tom Lendacky
2020-11-10 17:50 ` Thomas Gleixner
2020-11-10 18:56 ` Thomas Gleixner
2020-11-10 19:21 ` David Woodhouse
2020-11-10 21:01 ` Thomas Gleixner
2020-11-10 21:30 ` David Woodhouse
2020-11-10 22:00 ` Tom Lendacky
2020-11-10 22:48 ` Thomas Gleixner
2020-11-10 23:05 ` Tom Lendacky
2020-11-11 8:16 ` David Woodhouse
2020-11-11 9:46 ` Thomas Gleixner
2020-11-11 10:36 ` David Woodhouse
2020-11-11 12:32 ` David Woodhouse
2020-11-11 20:30 ` Tom Lendacky
2020-11-11 21:19 ` David Woodhouse
2020-11-13 15:14 ` David Woodhouse
2020-11-16 18:02 ` David Woodhouse
2020-11-17 2:00 ` Suravee Suthikulpanit
2020-11-18 10:29 ` Suravee Suthikulpanit
2020-11-18 10:52 ` David Woodhouse
2020-11-18 14:06 ` Thomas Gleixner
2020-11-18 16:51 ` Suravee Suthikulpanit
2020-11-18 17:08 ` David Woodhouse
2020-11-18 20:16 ` [tip: x86/apic] iommu/amd: Fix IOMMU interrupt generation in X2APIC mode tip-bot2 for David Woodhouse
2020-11-11 14:43 ` [PATCH 1/3] iommu/amd: Don't register interrupt remapping irqdomain when IR is disabled David Woodhouse
2020-11-11 14:43 ` [PATCH 2/3] iommu/amd: Fix union of bitfields in intcapxt support David Woodhouse
2020-11-11 22:06 ` [tip: x86/apic] " tip-bot2 for David Woodhouse
2020-11-11 14:43 ` [PATCH 3/3] iommu/amd: Fix IOMMU interrupt generation in X2APIC mode David Woodhouse
2020-11-11 22:06 ` [tip: x86/apic] iommu/amd: Don't register interrupt remapping irqdomain when IR is disabled tip-bot2 for David Woodhouse
2020-11-10 17:47 ` [tip: x86/apic] x86/ioapic: Correct the PCI/ISA trigger type selection tip-bot2 for Thomas Gleixner
2020-11-10 6:31 ` [PATCH v3 19/35] x86/io_apic: Cleanup trigger/polarity helpers Qian Cai
2020-11-10 6:31 ` Qian Cai
2020-11-10 8:59 ` David Woodhouse
2020-11-10 8:59 ` David Woodhouse
2020-11-10 16:26 ` Paolo Bonzini
2020-11-10 16:26 ` Paolo Bonzini
2020-10-24 21:35 ` [PATCH v3 20/35] x86/ioapic: Cleanup IO/APIC route entry structs David Woodhouse
2020-10-24 21:35 ` David Woodhouse
2020-10-29 12:15 ` [tip: x86/apic] " tip-bot2 for Thomas Gleixner
2020-10-24 21:35 ` [PATCH v3 21/35] x86/ioapic: Generate RTE directly from parent irqchip's MSI message David Woodhouse
2020-10-24 21:35 ` David Woodhouse
2020-10-29 12:15 ` [tip: x86/apic] " tip-bot2 for David Woodhouse
2020-10-24 21:35 ` [PATCH v3 22/35] genirq/irqdomain: Implement get_name() method on irqchip fwnodes David Woodhouse
2020-10-24 21:35 ` David Woodhouse
2020-10-25 9:41 ` Marc Zyngier
2020-10-25 9:41 ` Marc Zyngier
2020-10-29 12:15 ` [tip: x86/apic] " tip-bot2 for David Woodhouse
2020-10-24 21:35 ` [PATCH v3 23/35] x86/apic: Add select() method on vector irqdomain David Woodhouse
2020-10-24 21:35 ` David Woodhouse
2020-10-29 12:15 ` [tip: x86/apic] " tip-bot2 for David Woodhouse
2020-10-24 21:35 ` [PATCH v3 24/35] iommu/amd: Implement select() method on remapping irqdomain David Woodhouse
2020-10-24 21:35 ` David Woodhouse
2020-10-29 12:15 ` [tip: x86/apic] " tip-bot2 for David Woodhouse
2020-10-24 21:35 ` [PATCH v3 25/35] iommu/vt-d: " David Woodhouse
2020-10-24 21:35 ` David Woodhouse
2020-10-29 12:15 ` [tip: x86/apic] " tip-bot2 for David Woodhouse
2020-10-24 21:35 ` [PATCH v3 26/35] iommu/hyper-v: " David Woodhouse
2020-10-24 21:35 ` David Woodhouse
2020-10-29 12:15 ` [tip: x86/apic] " tip-bot2 for David Woodhouse
2020-10-24 21:35 ` [PATCH v3 27/35] x86/hpet: Use irq_find_matching_fwspec() to find " David Woodhouse
2020-10-24 21:35 ` David Woodhouse
2020-10-29 12:15 ` [tip: x86/apic] " tip-bot2 for David Woodhouse
2020-10-24 21:35 ` [PATCH v3 28/35] x86/ioapic: " David Woodhouse
2020-10-24 21:35 ` David Woodhouse
2020-10-29 12:15 ` [tip: x86/apic] " tip-bot2 for David Woodhouse
2020-10-24 21:35 ` [PATCH v3 29/35] x86: Kill all traces of irq_remapping_get_irq_domain() David Woodhouse
2020-10-24 21:35 ` David Woodhouse
2020-10-29 12:15 ` [tip: x86/apic] " tip-bot2 for David Woodhouse
2020-10-24 21:35 ` [PATCH v3 30/35] iommu/vt-d: Simplify intel_irq_remapping_select() David Woodhouse
2020-10-24 21:35 ` David Woodhouse
2020-10-29 12:15 ` [tip: x86/apic] " tip-bot2 for David Woodhouse
2020-10-24 21:35 ` [PATCH v3 31/35] x86/ioapic: Handle Extended Destination ID field in RTE David Woodhouse
2020-10-24 21:35 ` David Woodhouse
2020-10-29 12:15 ` [tip: x86/apic] " tip-bot2 for David Woodhouse
2020-10-24 21:35 ` [PATCH v3 32/35] x86/apic: Support 15 bits of APIC ID in MSI where available David Woodhouse
2020-10-24 21:35 ` David Woodhouse
2020-10-29 12:15 ` [tip: x86/apic] " tip-bot2 for David Woodhouse
2020-10-24 21:35 ` [PATCH v3 33/35] iommu/hyper-v: Disable IRQ pseudo-remapping if 15 bit APIC IDs are available David Woodhouse
2020-10-24 21:35 ` David Woodhouse
2020-10-29 12:15 ` [tip: x86/apic] " tip-bot2 for David Woodhouse
2020-10-24 21:35 ` [PATCH v3 34/35] x86/kvm: Reserve KVM_FEATURE_MSI_EXT_DEST_ID David Woodhouse
2020-10-24 21:35 ` David Woodhouse
2020-10-24 21:35 ` [PATCH v3 35/35] x86/kvm: Enable 15-bit extension when KVM_FEATURE_MSI_EXT_DEST_ID detected David Woodhouse
2020-10-24 21:35 ` David Woodhouse
2020-10-29 12:15 ` [tip: x86/apic] " tip-bot2 for David Woodhouse
2020-10-25 8:12 ` [PATCH v3 00/35] Fix x2apic enablement and allow more CPUs, clean up I/OAPIC and MSI bitfields David Woodhouse
2020-10-25 8:12 ` David Woodhouse
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