From: Weihang Li <liweihang@huawei.com>
To: <dledford@redhat.com>, <jgg@nvidia.com>
Cc: <leon@kernel.org>, <linux-rdma@vger.kernel.org>,
<linuxarm@openeuler.org>
Subject: [PATCH for-next 01/12] RDMA/hns: Avoid filling sgid index when modifying QP to RTR
Date: Fri, 5 Feb 2021 17:39:23 +0800 [thread overview]
Message-ID: <1612517974-31867-2-git-send-email-liweihang@huawei.com> (raw)
In-Reply-To: <1612517974-31867-1-git-send-email-liweihang@huawei.com>
ULP usually set IB(V)_QP_AV when trying to modify QP to RTR if they want
to record sgid index into QPC. For UD QPs, it is useless because it will be
included in WQE. For RC QPs, it will be filled in hns_roce_set_path(). So
sgid index shouldn't be filled by default. Then hns_get_gid_index() is
moved to hns_roce_hw_v1.c because it is only called in it.
Fixes: 926a01dc000d ("RDMA/hns: Add QP operations support for hip08 SoC")
Signed-off-by: Weihang Li <liweihang@huawei.com>
---
drivers/infiniband/hw/hns/hns_roce_hw_v1.c | 16 ++++++++++++++++
drivers/infiniband/hw/hns/hns_roce_hw_v2.c | 11 -----------
drivers/infiniband/hw/hns/hns_roce_main.c | 16 ----------------
3 files changed, 16 insertions(+), 27 deletions(-)
diff --git a/drivers/infiniband/hw/hns/hns_roce_hw_v1.c b/drivers/infiniband/hw/hns/hns_roce_hw_v1.c
index 23fe8e9..262ad58 100644
--- a/drivers/infiniband/hw/hns/hns_roce_hw_v1.c
+++ b/drivers/infiniband/hw/hns/hns_roce_hw_v1.c
@@ -43,6 +43,22 @@
#include "hns_roce_hem.h"
#include "hns_roce_hw_v1.h"
+/**
+ * hns_get_gid_index - Get gid index.
+ * @hr_dev: pointer to structure hns_roce_dev.
+ * @port: port, value range: 0 ~ MAX
+ * @gid_index: gid_index, value range: 0 ~ MAX
+ * Description:
+ * N ports shared gids, allocation method as follow:
+ * GID[0][0], GID[1][0],.....GID[N - 1][0],
+ * GID[0][0], GID[1][0],.....GID[N - 1][0],
+ * And so on
+ */
+u8 hns_get_gid_index(struct hns_roce_dev *hr_dev, u8 port, int gid_index)
+{
+ return gid_index * hr_dev->caps.num_ports + port;
+}
+
static void set_data_seg(struct hns_roce_wqe_data_seg *dseg, struct ib_sge *sg)
{
dseg->lkey = cpu_to_le32(sg->lkey);
diff --git a/drivers/infiniband/hw/hns/hns_roce_hw_v2.c b/drivers/infiniband/hw/hns/hns_roce_hw_v2.c
index c962f26..f0691f4 100644
--- a/drivers/infiniband/hw/hns/hns_roce_hw_v2.c
+++ b/drivers/infiniband/hw/hns/hns_roce_hw_v2.c
@@ -4308,7 +4308,6 @@ static int modify_qp_init_to_rtr(struct ib_qp *ibqp,
struct hns_roce_v2_qp_context *context,
struct hns_roce_v2_qp_context *qpc_mask)
{
- const struct ib_global_route *grh = rdma_ah_read_grh(&attr->ah_attr);
struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
struct ib_device *ibdev = &hr_dev->ib_dev;
@@ -4316,7 +4315,6 @@ static int modify_qp_init_to_rtr(struct ib_qp *ibqp,
dma_addr_t irrl_ba;
enum ib_mtu mtu;
u8 lp_pktn_ini;
- u8 port_num;
u64 *mtts;
u8 *dmac;
u8 *smac;
@@ -4397,15 +4395,6 @@ static int modify_qp_init_to_rtr(struct ib_qp *ibqp,
V2_QPC_BYTE_56_DQPN_M, V2_QPC_BYTE_56_DQPN_S, 0);
}
- /* Configure GID index */
- port_num = rdma_ah_get_port_num(&attr->ah_attr);
- roce_set_field(context->byte_20_smac_sgid_idx,
- V2_QPC_BYTE_20_SGID_IDX_M, V2_QPC_BYTE_20_SGID_IDX_S,
- hns_get_gid_index(hr_dev, port_num - 1,
- grh->sgid_index));
- roce_set_field(qpc_mask->byte_20_smac_sgid_idx,
- V2_QPC_BYTE_20_SGID_IDX_M, V2_QPC_BYTE_20_SGID_IDX_S, 0);
-
memcpy(&(context->dmac), dmac, sizeof(u32));
roce_set_field(context->byte_52_udpspn_dmac, V2_QPC_BYTE_52_DMAC_M,
V2_QPC_BYTE_52_DMAC_S, *((u16 *)(&dmac[4])));
diff --git a/drivers/infiniband/hw/hns/hns_roce_main.c b/drivers/infiniband/hw/hns/hns_roce_main.c
index 7978220..c29215a 100644
--- a/drivers/infiniband/hw/hns/hns_roce_main.c
+++ b/drivers/infiniband/hw/hns/hns_roce_main.c
@@ -42,22 +42,6 @@
#include "hns_roce_device.h"
#include "hns_roce_hem.h"
-/**
- * hns_get_gid_index - Get gid index.
- * @hr_dev: pointer to structure hns_roce_dev.
- * @port: port, value range: 0 ~ MAX
- * @gid_index: gid_index, value range: 0 ~ MAX
- * Description:
- * N ports shared gids, allocation method as follow:
- * GID[0][0], GID[1][0],.....GID[N - 1][0],
- * GID[0][0], GID[1][0],.....GID[N - 1][0],
- * And so on
- */
-u8 hns_get_gid_index(struct hns_roce_dev *hr_dev, u8 port, int gid_index)
-{
- return gid_index * hr_dev->caps.num_ports + port;
-}
-
static int hns_roce_set_mac(struct hns_roce_dev *hr_dev, u8 port, u8 *addr)
{
u8 phy_port;
--
2.8.1
next prev parent reply other threads:[~2021-02-05 9:44 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-02-05 9:39 [PATCH for-next 00/12] RDMA/hns: Updates for 5.12 Weihang Li
2021-02-05 9:39 ` Weihang Li [this message]
2021-02-05 9:39 ` [PATCH for-next 02/12] RDMA/hns: Fix type of sq_signal_bits Weihang Li
2021-02-05 9:39 ` [PATCH for-next 03/12] RDMA/hns: Add mapped page count checking for MTR Weihang Li
2021-02-05 9:39 ` [PATCH for-next 04/12] RDMA/hns: Disable RQ inline by default Weihang Li
2021-02-05 9:39 ` [PATCH for-next 05/12] RDMA/hns: Adjust definition of FRMR fields Weihang Li
2021-02-09 0:23 ` Jason Gunthorpe
2021-02-09 7:56 ` liweihang
2021-02-05 9:39 ` [PATCH for-next 06/12] RDMA/hns: Skip qp_flow_control_init() for HIP09 Weihang Li
2021-02-05 9:39 ` [PATCH for-next 07/12] RDMA/hns: Replace wmb&__raw_writeq with writeq Weihang Li
2021-02-05 9:39 ` [PATCH for-next 08/12] RDMA/hns: Move HIP06 related definitions into hns_roce_hw_v1.h Weihang Li
2021-02-05 9:39 ` [PATCH for-next 09/12] RDMA/hns: Remove some magic numbers Weihang Li
2021-02-05 9:39 ` [PATCH for-next 10/12] RDMA/hns: Avoid unnecessary memset on WQEs in post_send Weihang Li
2021-02-05 9:39 ` [PATCH for-next 11/12] RDMA/hns: Remove unnecessary wrap around for EQ's consumer index Weihang Li
2021-02-05 9:39 ` [PATCH for-next 12/12] RDMA/hns: Delete redundant judgment when preparing descriptors Weihang Li
2021-02-09 0:28 ` [PATCH for-next 00/12] RDMA/hns: Updates for 5.12 Jason Gunthorpe
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