From: Mark Brown <broonie@kernel.org>
To: perex@perex.cz, alsa-devel@alsa-project.org,
peter.ujfalusi@ti.com, kuninori.morimoto.gx@renesas.com,
tiwai@suse.com, linux-kernel@vger.kernel.org,
pierre-louis.bossart@linux.intel.com, lgirdwood@gmail.com,
patches@opensource.cirrus.com, daniel.baluta@nxp.com,
gustavoars@kernel.org, ckeepax@opensource.cirrus.com,
Shengjiu Wang <shengjiu.wang@nxp.com>
Cc: Mark Brown <broonie@kernel.org>
Subject: Re: [PATCH] ASoC: wm8960: Fix wrong bclk and lrclk with pll enabled for some chips
Date: Tue, 23 Mar 2021 22:12:14 +0000 [thread overview]
Message-ID: <161653747938.32729.14710605922324529557.b4-ty@kernel.org> (raw)
In-Reply-To: <1616150926-22892-1-git-send-email-shengjiu.wang@nxp.com>
On Fri, 19 Mar 2021 18:48:46 +0800, Shengjiu Wang wrote:
> The input MCLK is 12.288MHz, the desired output sysclk is 11.2896MHz
> and sample rate is 44100Hz, with the configuration pllprescale=2,
> postscale=sysclkdiv=1, some chip may have wrong bclk
> and lrclk output with pll enabled in master mode, but with the
> configuration pllprescale=1, postscale=2, the output clock is correct.
>
> >From Datasheet, the PLL performs best when f2 is between
> 90MHz and 100MHz when the desired sysclk output is 11.2896MHz
> or 12.288MHz, so sysclkdiv = 2 (f2/8) is the best choice.
>
> [...]
Applied to
https://git.kernel.org/pub/scm/linux/kernel/git/broonie/sound.git for-next
Thanks!
[1/1] ASoC: wm8960: Fix wrong bclk and lrclk with pll enabled for some chips
commit: 16b82e75c15a7dbd564ea3654f3feb61df9e1e6f
All being well this means that it will be integrated into the linux-next
tree (usually sometime in the next 24 hours) and sent to Linus during
the next merge window (or sooner if it is a bug fix), however if
problems are discovered then the patch may be dropped or reverted.
You may get further e-mails resulting from automated or manual testing
and review of the tree, please engage with people reporting problems and
send followup patches addressing any issues that are reported if needed.
If any updates are required or you are submitting further changes they
should be sent as incremental updates against current git, existing
patches will not be replaced.
Please add any relevant lists and maintainers to the CCs when replying
to this mail.
Thanks,
Mark
prev parent reply other threads:[~2021-03-23 22:13 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-03-19 10:48 [PATCH] ASoC: wm8960: Fix wrong bclk and lrclk with pll enabled for some chips Shengjiu Wang
2021-03-23 9:59 ` Charles Keepax
2021-03-23 9:59 ` Charles Keepax
2021-03-23 22:12 ` Mark Brown [this message]
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