From: Yang Weijiang <weijiang.yang@intel.com>
To: pbonzini@redhat.com, jmattson@google.com, seanjc@google.com,
vkuznets@redhat.com, wei.w.wang@intel.com,
like.xu.linux@gmail.com, kvm@vger.kernel.org,
linux-kernel@vger.kernel.org
Cc: Like Xu <like.xu@linux.intel.com>,
Yang Weijiang <weijiang.yang@intel.com>
Subject: [PATCH v6 10/12] KVM: x86: Add XSAVE Support for Architectural LBR
Date: Fri, 16 Jul 2021 16:50:04 +0800 [thread overview]
Message-ID: <1626425406-18582-11-git-send-email-weijiang.yang@intel.com> (raw)
In-Reply-To: <1626425406-18582-1-git-send-email-weijiang.yang@intel.com>
From: Like Xu <like.xu@linux.intel.com>
On processors supporting XSAVES and XRSTORS, Architectural LBR XSAVE
support is enumerated from CPUID.(EAX=0DH, ECX=1):ECX[bit 15].
The detailed sub-leaf for Arch LBR is enumerated in CPUID.(0DH, 0FH).
XSAVES provides a faster means than RDMSR for guest to read all LBRs.
When guest IA32_XSS[bit 15] is set, the Arch LBR state can be saved using
XSAVES and restored by XRSTORS with the appropriate RFBM.
Signed-off-by: Like Xu <like.xu@linux.intel.com>
Signed-off-by: Yang Weijiang <weijiang.yang@intel.com>
---
arch/x86/kvm/vmx/vmx.c | 4 ++++
arch/x86/kvm/x86.c | 2 +-
2 files changed, 5 insertions(+), 1 deletion(-)
diff --git a/arch/x86/kvm/vmx/vmx.c b/arch/x86/kvm/vmx/vmx.c
index 3815a32166a6..81d7a300fb6c 100644
--- a/arch/x86/kvm/vmx/vmx.c
+++ b/arch/x86/kvm/vmx/vmx.c
@@ -7314,6 +7314,10 @@ static __init void vmx_set_cpu_caps(void)
kvm_cpu_cap_clear(X86_FEATURE_INVPCID);
if (vmx_pt_mode_is_host_guest())
kvm_cpu_cap_check_and_set(X86_FEATURE_INTEL_PT);
+ if (!cpu_has_vmx_arch_lbr()) {
+ kvm_cpu_cap_clear(X86_FEATURE_ARCH_LBR);
+ supported_xss &= ~XFEATURE_MASK_LBR;
+ }
if (!enable_sgx) {
kvm_cpu_cap_clear(X86_FEATURE_SGX);
diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c
index 2424d475a4d7..c09522c1f3ec 100644
--- a/arch/x86/kvm/x86.c
+++ b/arch/x86/kvm/x86.c
@@ -203,7 +203,7 @@ static struct kvm_user_return_msrs __percpu *user_return_msrs;
| XFEATURE_MASK_BNDCSR | XFEATURE_MASK_AVX512 \
| XFEATURE_MASK_PKRU)
-#define KVM_SUPPORTED_XSS 0
+#define KVM_SUPPORTED_XSS XFEATURE_MASK_LBR
u64 __read_mostly host_efer;
EXPORT_SYMBOL_GPL(host_efer);
--
2.21.1
next prev parent reply other threads:[~2021-07-16 8:37 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-07-16 8:49 [PATCH v6 00/12] Introduce Architectural LBR for vPMU Yang Weijiang
2021-07-16 8:49 ` [PATCH v6 01/12] perf/x86/intel: Fix the comment about guest LBR support on KVM Yang Weijiang
2021-07-16 8:49 ` [PATCH v6 02/12] perf/x86/lbr: Simplify the exposure check for the LBR_INFO registers Yang Weijiang
2021-07-16 8:49 ` [PATCH v6 03/12] KVM: x86: Add Arch LBR MSRs to msrs_to_save_all list Yang Weijiang
2021-07-16 8:49 ` [PATCH v6 04/12] KVM: vmx/pmu: Emulate MSR_ARCH_LBR_DEPTH for guest Arch LBR Yang Weijiang
2021-07-16 23:33 ` Jim Mattson
2021-07-19 7:27 ` Yang Weijiang
2021-07-16 8:49 ` [PATCH v6 05/12] KVM: vmx/pmu: Emulate MSR_ARCH_LBR_CTL " Yang Weijiang
2021-07-16 8:50 ` [PATCH v6 06/12] KVM: x86/pmu: Refactor code to support " Yang Weijiang
2021-07-16 8:50 ` [PATCH v6 07/12] KVM: x86: Refresh CPUID on writes to MSR_IA32_XSS Yang Weijiang
2021-07-16 8:50 ` [PATCH v6 08/12] KVM: x86: Report XSS as an MSR to be saved if there are supported features Yang Weijiang
2021-07-16 8:50 ` [PATCH v6 09/12] KVM: x86: Refine the matching and clearing logic for supported_xss Yang Weijiang
2021-07-16 8:50 ` Yang Weijiang [this message]
2021-07-16 8:50 ` [PATCH v6 11/12] KVM: x86/vmx: Check Arch LBR config when return perf capabilities Yang Weijiang
2021-07-16 8:50 ` [PATCH v6 12/12] KVM: x86/cpuid: Advise Arch LBR feature in CPUID Yang Weijiang
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