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From: Dan Williams <dan.j.williams@intel.com>
To: linux-cxl@vger.kernel.org
Cc: Ben Widawsky <ben.widawsky@intel.com>,
	alison.schofield@intel.com, ben.widawsky@intel.com,
	Jonathan.Cameron@huawei.com
Subject: [PATCH 6/6] cxl/registers: Fix Documentation warning
Date: Fri, 03 Sep 2021 19:21:06 -0700	[thread overview]
Message-ID: <163072206675.2250120.3527179192933919995.stgit@dwillia2-desk3.amr.corp.intel.com> (raw)
In-Reply-To: <163072203373.2250120.8373702699578427249.stgit@dwillia2-desk3.amr.corp.intel.com>

Commit 0f06157e0135 ("cxl/core: Move register mapping infrastructure")
neglected to add a DOC header for the new drivers/core/regs.c file.

Reported-by: Ben Widawsky <ben.widawsky@intel.com>
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
---
 Documentation/driver-api/cxl/memory-devices.rst |    2 +-
 drivers/cxl/core/regs.c                         |   15 ++++++++++++++-
 2 files changed, 15 insertions(+), 2 deletions(-)

diff --git a/Documentation/driver-api/cxl/memory-devices.rst b/Documentation/driver-api/cxl/memory-devices.rst
index df799cdf1c3f..50ebcda17ad0 100644
--- a/Documentation/driver-api/cxl/memory-devices.rst
+++ b/Documentation/driver-api/cxl/memory-devices.rst
@@ -43,7 +43,7 @@ CXL Core
    :doc: cxl pmem
 
 .. kernel-doc:: drivers/cxl/core/regs.c
-   :internal:
+   :doc: cxl registers
 
 External Interfaces
 ===================
diff --git a/drivers/cxl/core/regs.c b/drivers/cxl/core/regs.c
index 8535a7b94f28..41de4a136ecd 100644
--- a/drivers/cxl/core/regs.c
+++ b/drivers/cxl/core/regs.c
@@ -1,12 +1,25 @@
 // SPDX-License-Identifier: GPL-2.0-only
 /* Copyright(c) 2020 Intel Corporation. */
-
 #include <linux/io-64-nonatomic-lo-hi.h>
 #include <linux/device.h>
 #include <linux/slab.h>
 #include <linux/pci.h>
 #include <cxlmem.h>
 
+/**
+ * DOC: cxl registers
+ *
+ * CXL device capabilities are enumerated by PCI DVSEC (Designated
+ * Vendor-specific) and / or descriptors provided by platform firmware.
+ * They can be defined as a set like the device and component registers
+ * mandated by CXL Section 8.1.12.2 Memory Device PCIe Capabilities and
+ * Extended Capabilities, or they can be individual capabilities
+ * appended to bridged and endpoint devices.
+ *
+ * Provide common infrastructure for enumerating and mapping these
+ * discrete capabilities.
+ */
+
 /**
  * cxl_probe_component_regs() - Detect CXL Component register blocks
  * @dev: Host device of the @base mapping


  parent reply	other threads:[~2021-09-04  2:21 UTC|newest]

Thread overview: 17+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-09-04  2:20 [PATCH 0/6] cxl fixes for v5.15-rc1 Dan Williams
2021-09-04  2:20 ` [PATCH 1/6] cxl/acpi: Do not add DSDT disabled ACPI0016 host bridge ports Dan Williams
2021-09-04  2:20 ` [PATCH 2/6] cxl/pci: Fix lockdown level Dan Williams
2021-09-04  3:57   ` Paul Moore
2021-09-07 17:38     ` Dan Williams
2021-09-07 19:46       ` Paul Moore
2021-09-10 12:55         ` Ondrej Mosnacek
2021-09-10 14:56           ` Dan Williams
2021-09-10 17:46           ` Paul Moore
2021-09-04  2:20 ` [PATCH 3/6] cxl/pci: Fix debug message in cxl_probe_regs() Dan Williams
2021-09-06  9:04   ` Jonathan Cameron
2021-09-04  2:20 ` [PATCH 4/6] cxl/uapi: Fix defined but not used warnings Dan Williams
2021-09-06  9:05   ` Jonathan Cameron
2021-09-04  2:21 ` [PATCH 5/6] cxl/pmem: Fix Documentation warning Dan Williams
2021-09-06  9:08   ` Jonathan Cameron
2021-09-04  2:21 ` Dan Williams [this message]
2021-09-06  9:10   ` [PATCH 6/6] cxl/registers: " Jonathan Cameron

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