From: Patchwork <patchwork@emeril.freedesktop.org>
To: "Matthew Brost" <matthew.brost@intel.com>
Cc: intel-gfx@lists.freedesktop.org
Subject: [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Parallel submission aka multi-bb execbuf (rev6)
Date: Wed, 13 Oct 2021 21:40:31 -0000 [thread overview]
Message-ID: <163416123188.10254.16524381483196937436@emeril.freedesktop.org> (raw)
In-Reply-To: <20211013204231.19287-1-matthew.brost@intel.com>
== Series Details ==
Series: Parallel submission aka multi-bb execbuf (rev6)
URL : https://patchwork.freedesktop.org/series/92789/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
96b392951d3d drm/i915/guc: Move GuC guc_id allocation under submission state sub-struct
a7d1c1c82188 drm/i915/guc: Take GT PM ref when deregistering context
-:82: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'gt' - possible side-effects?
#82: FILE: drivers/gpu/drm/i915/gt/intel_gt_pm.h:44:
+#define with_intel_gt_pm(gt, tmp) \
+ for (tmp = 1, intel_gt_pm_get(gt); tmp; \
+ intel_gt_pm_put(gt), tmp = 0)
-:82: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'tmp' - possible side-effects?
#82: FILE: drivers/gpu/drm/i915/gt/intel_gt_pm.h:44:
+#define with_intel_gt_pm(gt, tmp) \
+ for (tmp = 1, intel_gt_pm_get(gt); tmp; \
+ intel_gt_pm_put(gt), tmp = 0)
total: 0 errors, 0 warnings, 2 checks, 290 lines checked
fce1426ce7b7 drm/i915/guc: Take engine PM when a context is pinned with GuC submission
7751cb08a525 drm/i915/guc: Don't call switch_to_kernel_context with GuC submission
edf6b764f7ad drm/i915: Add logical engine mapping
baf5dc1fc9df drm/i915: Expose logical engine instance to user
3fcd1f83dde6 drm/i915/guc: Introduce context parent-child relationship
150093ea7387 drm/i915/guc: Add multi-lrc context registration
0d569f349c42 drm/i915/guc: Ensure GuC schedule operations do not operate on child contexts
0bdfa5c16cbe drm/i915/guc: Assign contexts in parent-child relationship consecutive guc_ids
15aba0f8dc81 drm/i915/guc: Implement parallel context pin / unpin functions
13fb055cc22c drm/i915/guc: Implement multi-lrc submission
-:394: CHECK:SPACING: spaces preferred around that '*' (ctx:ExV)
#394: FILE: drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c:775:
+ *wqi++ = child->ring->tail / sizeof(u64);
^
total: 0 errors, 0 warnings, 1 checks, 597 lines checked
31917c1dcf79 drm/i915/guc: Insert submit fences between requests in parent-child relationship
cc32a9e001af drm/i915/guc: Implement multi-lrc reset
fc3628d02c3a drm/i915/guc: Update debugfs for GuC multi-lrc
a6dbcce14531 drm/i915/guc: Connect UAPI to GuC multi-lrc interface
304fa81a9399 drm/i915/doc: Update parallel submit doc to point to i915_drm.h
-:13: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating?
#13:
deleted file mode 100644
total: 0 errors, 1 warnings, 0 checks, 10 lines checked
27d342e07431 drm/i915/guc: Add basic GuC multi-lrc selftest
-:22: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating?
#22:
new file mode 100644
total: 0 errors, 1 warnings, 0 checks, 190 lines checked
1984b91d5186 drm/i915/guc: Implement no mid batch preemption for multi-lrc
f5b8b45334d5 drm/i915: Multi-BB execbuf
-:381: CHECK:MACRO_ARG_REUSE: Macro argument reuse '_i' - possible side-effects?
#381: FILE: drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c:1874:
+#define for_each_batch_create_order(_eb, _i) \
+ for ((_i) = 0; (_i) < (_eb)->num_batches; ++(_i))
-:383: ERROR:MULTISTATEMENT_MACRO_USE_DO_WHILE: Macros with multiple statements should be enclosed in a do - while loop
#383: FILE: drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c:1876:
+#define for_each_batch_add_order(_eb, _i) \
+ BUILD_BUG_ON(!typecheck(int, _i)); \
+ for ((_i) = (_eb)->num_batches - 1; (_i) >= 0; --(_i))
-:383: CHECK:MACRO_ARG_REUSE: Macro argument reuse '_i' - possible side-effects?
#383: FILE: drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c:1876:
+#define for_each_batch_add_order(_eb, _i) \
+ BUILD_BUG_ON(!typecheck(int, _i)); \
+ for ((_i) = (_eb)->num_batches - 1; (_i) >= 0; --(_i))
total: 1 errors, 0 warnings, 2 checks, 1289 lines checked
5370262c7b18 drm/i915/guc: Handle errors in multi-lrc requests
45927bbbecde drm/i915: Make request conflict tracking understand parallel submits
20f16cbe9cab drm/i915: Update I915_GEM_BUSY IOCTL to understand composite fences
1f94d4826235 drm/i915: Enable multi-bb execbuf
9a0c2d682fa1 drm/i915/execlists: Weak parallel submission support for execlists
next prev parent reply other threads:[~2021-10-13 21:40 UTC|newest]
Thread overview: 94+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-10-13 20:42 [PATCH 00/25] Parallel submission aka multi-bb execbuf Matthew Brost
2021-10-13 20:42 ` [Intel-gfx] " Matthew Brost
2021-10-13 20:42 ` [Intel-gfx] [PATCH 01/25] drm/i915/guc: Move GuC guc_id allocation under submission state sub-struct Matthew Brost
2021-10-13 20:42 ` Matthew Brost
2021-10-13 23:56 ` John Harrison
2021-10-13 23:56 ` [Intel-gfx] " John Harrison
2021-10-13 20:42 ` [PATCH 02/25] drm/i915/guc: Take GT PM ref when deregistering context Matthew Brost
2021-10-13 20:42 ` [Intel-gfx] " Matthew Brost
2021-10-13 23:59 ` John Harrison
2021-10-13 23:59 ` [Intel-gfx] " John Harrison
2021-10-13 20:42 ` [PATCH 03/25] drm/i915/guc: Take engine PM when a context is pinned with GuC submission Matthew Brost
2021-10-13 20:42 ` [Intel-gfx] " Matthew Brost
2021-10-14 0:05 ` John Harrison
2021-10-14 0:05 ` [Intel-gfx] " John Harrison
2021-10-13 20:42 ` [PATCH 04/25] drm/i915/guc: Don't call switch_to_kernel_context " Matthew Brost
2021-10-13 20:42 ` [Intel-gfx] " Matthew Brost
2021-10-13 20:42 ` [Intel-gfx] [PATCH 05/25] drm/i915: Add logical engine mapping Matthew Brost
2021-10-13 20:42 ` Matthew Brost
2021-10-13 20:42 ` [Intel-gfx] [PATCH 06/25] drm/i915: Expose logical engine instance to user Matthew Brost
2021-10-13 20:42 ` Matthew Brost
2021-10-13 20:42 ` [Intel-gfx] [PATCH 07/25] drm/i915/guc: Introduce context parent-child relationship Matthew Brost
2021-10-13 20:42 ` Matthew Brost
2021-10-13 20:42 ` [PATCH 08/25] drm/i915/guc: Add multi-lrc context registration Matthew Brost
2021-10-13 20:42 ` [Intel-gfx] " Matthew Brost
2021-10-14 0:10 ` John Harrison
2021-10-14 0:10 ` [Intel-gfx] " John Harrison
2021-10-14 4:26 ` Matthew Brost
2021-10-14 4:26 ` [Intel-gfx] " Matthew Brost
2021-10-13 20:42 ` [Intel-gfx] [PATCH 09/25] drm/i915/guc: Ensure GuC schedule operations do not operate on child contexts Matthew Brost
2021-10-13 20:42 ` Matthew Brost
2021-10-13 20:42 ` [PATCH 10/25] drm/i915/guc: Assign contexts in parent-child relationship consecutive guc_ids Matthew Brost
2021-10-13 20:42 ` [Intel-gfx] " Matthew Brost
2021-10-13 20:42 ` [PATCH 11/25] drm/i915/guc: Implement parallel context pin / unpin functions Matthew Brost
2021-10-13 20:42 ` [Intel-gfx] " Matthew Brost
2021-10-14 16:56 ` John Harrison
2021-10-14 16:56 ` [Intel-gfx] " John Harrison
2021-10-13 20:42 ` [PATCH 12/25] drm/i915/guc: Implement multi-lrc submission Matthew Brost
2021-10-13 20:42 ` [Intel-gfx] " Matthew Brost
2021-10-14 0:25 ` John Harrison
2021-10-14 0:25 ` John Harrison
2021-10-13 20:42 ` [PATCH 13/25] drm/i915/guc: Insert submit fences between requests in parent-child relationship Matthew Brost
2021-10-13 20:42 ` [Intel-gfx] " Matthew Brost
2021-10-13 20:42 ` [PATCH 14/25] drm/i915/guc: Implement multi-lrc reset Matthew Brost
2021-10-13 20:42 ` [Intel-gfx] " Matthew Brost
2021-10-14 0:28 ` John Harrison
2021-10-14 0:28 ` [Intel-gfx] " John Harrison
2021-10-14 16:26 ` kernel test robot
2021-10-14 16:26 ` kernel test robot
2021-10-14 16:26 ` [Intel-gfx] " kernel test robot
2021-10-13 20:42 ` [Intel-gfx] [PATCH 15/25] drm/i915/guc: Update debugfs for GuC multi-lrc Matthew Brost
2021-10-13 20:42 ` Matthew Brost
2021-10-13 20:42 ` [PATCH 16/25] drm/i915/guc: Connect UAPI to GuC multi-lrc interface Matthew Brost
2021-10-13 20:42 ` [Intel-gfx] " Matthew Brost
2021-10-14 1:02 ` John Harrison
2021-10-14 1:02 ` [Intel-gfx] " John Harrison
2021-10-14 15:32 ` Matthew Brost
2021-10-14 15:32 ` [Intel-gfx] " Matthew Brost
2021-10-14 16:43 ` John Harrison
2021-10-14 16:43 ` [Intel-gfx] " John Harrison
2021-10-14 16:41 ` Matthew Brost
2021-10-14 16:41 ` Matthew Brost
2021-10-14 17:15 ` John Harrison
2021-10-14 17:15 ` [Intel-gfx] " John Harrison
2021-10-13 20:42 ` [PATCH 17/25] drm/i915/doc: Update parallel submit doc to point to i915_drm.h Matthew Brost
2021-10-13 20:42 ` [Intel-gfx] " Matthew Brost
2021-10-13 20:42 ` [PATCH 18/25] drm/i915/guc: Add basic GuC multi-lrc selftest Matthew Brost
2021-10-13 20:42 ` [Intel-gfx] " Matthew Brost
2021-10-13 20:42 ` [Intel-gfx] [PATCH 19/25] drm/i915/guc: Implement no mid batch preemption for multi-lrc Matthew Brost
2021-10-13 20:42 ` Matthew Brost
2021-10-14 0:48 ` John Harrison
2021-10-14 0:48 ` [Intel-gfx] " John Harrison
2021-10-13 20:42 ` [Intel-gfx] [PATCH 20/25] drm/i915: Multi-BB execbuf Matthew Brost
2021-10-13 20:42 ` Matthew Brost
2021-10-14 0:55 ` John Harrison
2021-10-14 0:55 ` [Intel-gfx] " John Harrison
2021-10-14 15:34 ` Matthew Brost
2021-10-14 15:34 ` [Intel-gfx] " Matthew Brost
2021-10-13 20:42 ` [PATCH 21/25] drm/i915/guc: Handle errors in multi-lrc requests Matthew Brost
2021-10-13 20:42 ` [Intel-gfx] " Matthew Brost
2021-10-14 0:57 ` John Harrison
2021-10-14 0:57 ` [Intel-gfx] " John Harrison
2021-10-13 20:42 ` [PATCH 22/25] drm/i915: Make request conflict tracking understand parallel submits Matthew Brost
2021-10-13 20:42 ` [Intel-gfx] " Matthew Brost
2021-10-14 0:59 ` John Harrison
2021-10-14 0:59 ` [Intel-gfx] " John Harrison
2021-10-13 20:42 ` [Intel-gfx] [PATCH 23/25] drm/i915: Update I915_GEM_BUSY IOCTL to understand composite fences Matthew Brost
2021-10-13 20:42 ` Matthew Brost
2021-10-13 20:42 ` [PATCH 24/25] drm/i915: Enable multi-bb execbuf Matthew Brost
2021-10-13 20:42 ` [Intel-gfx] " Matthew Brost
2021-10-13 20:42 ` [PATCH 25/25] drm/i915/execlists: Weak parallel submission support for execlists Matthew Brost
2021-10-13 20:42 ` [Intel-gfx] " Matthew Brost
2021-10-13 21:40 ` Patchwork [this message]
2021-10-13 21:42 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for Parallel submission aka multi-bb execbuf (rev6) Patchwork
2021-10-13 22:11 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
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