From: "irqchip-bot for Herve Codina" <tip-bot2@linutronix.de>
To: linux-kernel@vger.kernel.org
Cc: Herve Codina <herve.codina@bootlin.com>,
Linus Walleij <linus.walleij@linaro.org>,
Arnd Bergmann <arnd@arndb.de>,
Viresh Kumar <viresh.kumar@linaro.org>,
Marc Zyngier <maz@kernel.org>,
tglx@linutronix.de
Subject: [irqchip: irq/irqchip-next] irqchip/spear-shirq: Add support for IRQ 0..6
Date: Thu, 16 Dec 2021 15:24:46 -0000 [thread overview]
Message-ID: <163966828689.23020.13154863439448547706.tip-bot2@tip-bot2> (raw)
In-Reply-To: <20211202095255.165797-6-herve.codina@bootlin.com>
The following commit has been merged into the irq/irqchip-next branch of irqchip:
Commit-ID: f63c862587c9ba1c62de8c549e8f2fbe0fc88b6b
Gitweb: https://git.kernel.org/pub/scm/linux/kernel/git/maz/arm-platforms/f63c862587c9ba1c62de8c549e8f2fbe0fc88b6b
Author: Herve Codina <herve.codina@bootlin.com>
AuthorDate: Thu, 02 Dec 2021 10:52:54 +01:00
Committer: Marc Zyngier <maz@kernel.org>
CommitterDate: Thu, 16 Dec 2021 13:29:44
irqchip/spear-shirq: Add support for IRQ 0..6
IRQ 0..7 are not supported by the driver for SPEAr320 SOC family.
IRQ 0 is not reserved in SPEAr320 SOC (assigned to GPIOINT).
Furthermore, in SPEAr320s SOC variant, IRQ 0..6 are assigned
as follow:
IRQ 6 - NGPIO_INTR: Combined status of edge programmable
interrupts from GPIO ports
IRQ 5 - TX_OR_INTR: I2S interrupt on Transmit FIFO overrun
IRQ 4 - TX_EMP_INTR: I2S interrupt on Transmit FIFO empty
IRQ 3 - RX_OR_INTR: I2S interrupt on Receive FIFO overrun
IRQ 2 - RX_DA_INTR: I2S interrupt on data available in Receive FIFO
IRQ 1 - Reserved
IRQ 0 - GPIO_INTR: Legacy interrupt from GPIO ports
Add support for these IRQs in SPEAr320 SOC family.
Signed-off-by: Herve Codina <herve.codina@bootlin.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
Signed-off-by: Marc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/20211202095255.165797-6-herve.codina@bootlin.com
---
drivers/irqchip/spear-shirq.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/irqchip/spear-shirq.c b/drivers/irqchip/spear-shirq.c
index 1518ba3..7c17a6f 100644
--- a/drivers/irqchip/spear-shirq.c
+++ b/drivers/irqchip/spear-shirq.c
@@ -149,6 +149,8 @@ static struct spear_shirq spear320_shirq_ras3 = {
.offset = 0,
.nr_irqs = 7,
.mask = ((0x1 << 7) - 1) << 0,
+ .irq_chip = &dummy_irq_chip,
+ .status_reg = SPEAR320_INT_STS_MASK_REG,
};
static struct spear_shirq spear320_shirq_ras1 = {
next prev parent reply other threads:[~2021-12-16 15:24 UTC|newest]
Thread overview: 27+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-12-02 9:52 [PATCH 0/6] spear: Fix SPEAr3XX plgpio support Herve Codina
2021-12-02 9:52 ` Herve Codina
2021-12-02 9:52 ` [PATCH 1/6] pinctrl: spear: spear: Convert to regmap Herve Codina
2021-12-02 9:52 ` Herve Codina
2021-12-02 9:52 ` [PATCH 2/6] pinctrl: spear: plgpio: " Herve Codina
2021-12-02 9:52 ` Herve Codina
2021-12-02 9:52 ` [PATCH 3/6] pinctrl: spear: plgpio: Introduce regmap phandle Herve Codina
2021-12-02 9:52 ` Herve Codina
2021-12-02 9:52 ` [PATCH 4/6] ARM: dts: spear3xx: Use plgpio regmap in SPEAr310 and SPEAr320 Herve Codina
2021-12-02 9:52 ` Herve Codina
2021-12-02 9:52 ` [PATCH 5/6] irq: spear-shirq: Add support for IRQ 0..6 Herve Codina
2021-12-02 9:52 ` Herve Codina
2021-12-04 23:37 ` Linus Walleij
2021-12-04 23:37 ` Linus Walleij
2021-12-13 16:29 ` Arnd Bergmann
2021-12-13 16:29 ` Arnd Bergmann
2021-12-16 15:24 ` irqchip-bot for Herve Codina [this message]
2021-12-02 9:52 ` [PATCH 6/6] ARM: dts: spear3xx: Add spear320s dtsi Herve Codina
2021-12-02 9:52 ` Herve Codina
2021-12-02 11:27 ` [PATCH 0/6] spear: Fix SPEAr3XX plgpio support Viresh Kumar
2021-12-02 11:27 ` Viresh Kumar
2021-12-02 11:48 ` Herve Codina
2021-12-02 11:48 ` Herve Codina
2021-12-03 4:43 ` Viresh Kumar
2021-12-03 4:43 ` Viresh Kumar
2021-12-04 23:36 ` Linus Walleij
2021-12-04 23:36 ` Linus Walleij
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