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From: Dan Williams <dan.j.williams@intel.com>
To: linux-cxl@vger.kernel.org
Cc: Ira Weiny <ira.weiny@intel.com>,
	Jonathan Cameron <Jonathan.Cameron@huawei.com>
Subject: [PATCH v3 08/13] cxl/mem: Skip range enumeration if mem_enable clear
Date: Wed, 18 May 2022 16:34:54 -0700	[thread overview]
Message-ID: <165291689442.1426646.18012291761753694336.stgit@dwillia2-xfh> (raw)
In-Reply-To: <165291684910.1426646.8615474651213855015.stgit@dwillia2-xfh>

When a device does not have mem_enable set then the current range
settings are moot. Skip the enumeration and cause cxl_hdm_decode_init()
to proceed directly to enable the HDM Decoder Capability.

Fixes: 560f78559006 ("cxl/pci: Retrieve CXL DVSEC memory info")
Reviewed-by: Ira Weiny <ira.weiny@intel.com>
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
---
 drivers/cxl/core/pci.c |    2 ++
 drivers/cxl/mem.c      |    2 +-
 2 files changed, 3 insertions(+), 1 deletion(-)

diff --git a/drivers/cxl/core/pci.c b/drivers/cxl/core/pci.c
index ea6711721901..f3e59f8b6621 100644
--- a/drivers/cxl/core/pci.c
+++ b/drivers/cxl/core/pci.c
@@ -224,6 +224,8 @@ int cxl_dvsec_ranges(struct cxl_dev_state *cxlds,
 	}
 
 	info->mem_enabled = FIELD_GET(CXL_DVSEC_MEM_ENABLE, ctrl);
+	if (!info->mem_enabled)
+		return 0;
 
 	for (i = 0; i < hdm_count; i++) {
 		u64 base, size;
diff --git a/drivers/cxl/mem.c b/drivers/cxl/mem.c
index 0cfbde134fc7..902d1f6e189e 100644
--- a/drivers/cxl/mem.c
+++ b/drivers/cxl/mem.c
@@ -92,7 +92,7 @@ __mock bool cxl_hdm_decode_init(struct cxl_dev_state *cxlds,
 	 * are expected even though Linux does not require or maintain that
 	 * match.
 	 */
-	if (!global_enable && info->ranges)
+	if (!global_enable && info->mem_enabled && info->ranges)
 		goto out;
 
 	retval = true;


  parent reply	other threads:[~2022-05-18 23:34 UTC|newest]

Thread overview: 18+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-05-18 23:34 [PATCH v3 00/13] cxl: Fix "mem_enable" handling Dan Williams
2022-05-18 23:34 ` [PATCH v3 01/13] cxl/mem: Drop mem_enabled check from wait_for_media() Dan Williams
2022-05-18 23:34 ` [PATCH v3 02/13] cxl/pci: Consolidate wait_for_media() and wait_for_media_ready() Dan Williams
2022-05-18 23:34 ` [PATCH v3 03/13] cxl/pci: Drop wait_for_valid() from cxl_await_media_ready() Dan Williams
2022-05-18 23:34 ` [PATCH v3 04/13] cxl/mem: Fix cxl_mem_probe() error exit Dan Williams
2022-05-18 23:34 ` [PATCH v3 05/13] cxl/mem: Validate port connectivity before dvsec ranges Dan Williams
2022-05-18 23:34 ` [PATCH v3 06/13] cxl/pci: Move cxl_await_media_ready() to the core Dan Williams
2022-05-18 23:34 ` [PATCH v3 07/13] cxl/mem: Consolidate CXL DVSEC Range enumeration in " Dan Williams
2022-05-18 23:34 ` Dan Williams [this message]
2022-05-18 23:35 ` [PATCH v3 09/13] cxl/mem: Merge cxl_dvsec_ranges() and cxl_hdm_decode_init() Dan Williams
2022-05-18 23:35 ` [PATCH v3 10/13] cxl/pci: Drop @info argument to cxl_hdm_decode_init() Dan Williams
2022-05-18 23:35 ` [PATCH v3 11/13] cxl/port: Move endpoint HDM Decoder Capability init to port driver Dan Williams
2022-05-18 23:35 ` [PATCH v3 12/13] cxl/port: Reuse 'struct cxl_hdm' context for hdm init Dan Williams
2022-05-18 23:35 ` [PATCH v3 13/13] cxl/port: Enable HDM Capability after validating DVSEC Ranges Dan Williams
2022-05-19 22:38   ` [PATCH v4 " Dan Williams
2022-05-20 15:09     ` Jonathan Cameron
2022-05-20 17:35       ` Dan Williams
2022-05-20 18:30     ` [PATCH v5 " Dan Williams

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