Re: [PATCH v2] spi: cadence-quadspi: Disable irqs during indirect reads

From: Mark Brown <broonie@kernel.org>
To: Philipp Zabel <p.zabel@pengutronix.de>, niravkumar.l.rabara@intel.com
Cc: linux-kernel@vger.kernel.org, linux-spi@vger.kernel.org
Subject: Re: [PATCH v2] spi: cadence-quadspi: Disable irqs during indirect reads
Date: Mon, 22 Aug 2022 16:31:41 +0100	[thread overview]
Message-ID: <166118230149.175565.15964533101791462074.b4-ty@kernel.org> (raw)
In-Reply-To: <20220813042616.1372110-1-niravkumar.l.rabara@intel.com>

On Sat, 13 Aug 2022 12:26:16 +0800, niravkumar.l.rabara@intel.com wrote:
> From: Niravkumar L Rabara <niravkumar.l.rabara@intel.com>
> 
> On architecture where reading the SRAM is slower than the pace at
> controller fills it, with interrupt enabled while reading from
> SRAM FIFO causes unwanted interrupt storm to CPU.
> 
> The inner "bytes to read" loop never exits and waits for the completion
> so it is enough to only enable the watermark interrupt when we
> are out of bytes to read, which only happens when we start the
> transfer (waiting for the FIFO to fill up initially) if the SRAM
> is slow.
> 
> [...]

Applied to

   https://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi.git for-next

Thanks!

[1/1] spi: cadence-quadspi: Disable irqs during indirect reads
      commit: 9ee5b6d53b8c99d13a47227e3b7052a1365556c9

All being well this means that it will be integrated into the linux-next
tree (usually sometime in the next 24 hours) and sent to Linus during
the next merge window (or sooner if it is a bug fix), however if
problems are discovered then the patch may be dropped or reverted.

You may get further e-mails resulting from automated or manual testing
and review of the tree, please engage with people reporting problems and
send followup patches addressing any issues that are reported if needed.

If any updates are required or you are submitting further changes they
should be sent as incremental updates against current git, existing
patches will not be replaced.

Please add any relevant lists and maintainers to the CCs when replying
to this mail.

Thanks,
Mark