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From: Catalin Marinas <catalin.marinas@arm.com>
To: Will Deacon <will@kernel.org>, Marc Zyngier <maz@kernel.org>,
	Mark Rutland <mark.rutland@arm.com>,
	Andre Przywara <andre.przywara@arm.com>
Cc: Oliver Upton <oliver.upton@linux.dev>,
	James Morse <james.morse@arm.com>,
	Suzuki K Poulose <suzuki.poulose@arm.com>,
	Zenghui Yu <yuzenghui@huawei.com>,
	Daniel Lezcano <daniel.lezcano@linaro.org>,
	Thomas Gleixner <tglx@linutronix.de>,
	Rob Herring <robh@kernel.org>, Ross Burton <ross.burton@arm.com>,
	Khuong Dinh <khuong@os.amperecomputing.com>,
	Yang Shi <yang@os.amperecomputing.com>,
	D Scott Phillips <scott@os.amperecomputing.com>,
	Ilkka Koskinen <ilkka@os.amperecomputing.com>,
	Joe Korty <joe.korty@concurrent-rt.com>,
	linux-arm-kernel@lists.infradead.org,
	kvmarm@lists.cs.columbia.edu
Subject: Re: [PATCH] clocksource/drivers/arm_arch_timer: limit XGene-1 workaround
Date: Wed, 18 Oct 2023 11:15:07 +0100	[thread overview]
Message-ID: <169762410096.3624197.2312019285715198850.b4-ty@arm.com> (raw)
In-Reply-To: <20231016153127.116101-1-andre.przywara@arm.com>

On Mon, 16 Oct 2023 16:31:27 +0100, Andre Przywara wrote:
> The AppliedMicro XGene-1 CPU has an erratum where the timer condition
> would only consider TVAL, not CVAL. We currently apply a workaround when
> seeing the PartNum field of MIDR_EL1 being 0x000, under the assumption
> that this would match only the XGene-1 CPU model.
> However even the Ampere eMAG (aka XGene-3) uses that same part number, and
> only differs in the "Variant" and "Revision" fields: XGene-1's MIDR is
> 0x500f0000, our eMAG reports 0x503f0002. Experiments show the latter
> doesn't show the faulty behaviour.
> 
> [...]

Applied to arm64 (for-next/misc), thanks!

[1/1] clocksource/drivers/arm_arch_timer: limit XGene-1 workaround
      https://git.kernel.org/arm64/c/851354cbd12b

-- 
Catalin


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  parent reply	other threads:[~2023-10-18 10:15 UTC|newest]

Thread overview: 5+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-10-16 15:31 [PATCH] clocksource/drivers/arm_arch_timer: limit XGene-1 workaround Andre Przywara
2023-10-16 16:54 ` Marc Zyngier
2023-10-16 19:19 ` Oliver Upton
2023-10-18 10:15 ` Catalin Marinas [this message]
2023-10-24 14:58   ` Daniel Lezcano

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