From: "Heiko Stübner" <heiko@sntech.de>
To: Shunqian Zheng <zhengsq@rock-chips.com>
Cc: gregkh@linuxfoundation.org, srinivas.kandagatla@linaro.org,
maxime.ripard@free-electrons.com, caesar.wang@rock-chips.com,
dianders@chromium.org, linux-rockchip@lists.infradead.org,
linux-kernel@vger.kernel.org, xjq@rock-chips.com
Subject: Re: [PATCH v1 1/5] clk: rockchip: rk3288: Add the clock id of eFuse
Date: Tue, 11 Aug 2015 09:16:32 +0200 [thread overview]
Message-ID: <1757784.jPpHQAb5oi@diego> (raw)
In-Reply-To: <1439273706-28274-2-git-send-email-zhengsq@rock-chips.com>
Am Dienstag, 11. August 2015, 14:15:02 schrieb Shunqian Zheng:
> From: ZhengShunQian <zhengsq@rock-chips.com>
>
> The clock id is necessary item, changing it from 0
> then can be referred in driver and device tree.
>
> Signed-off-by: ZhengShunQian <zhengsq@rock-chips.com>
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
Patch is missing the clock maintainers and list
Mike Turquette <mturquette@baylibre.com>
Stephen Boyd <sboyd@codeaurora.org>
linux-clk@vger.kernel.org
> ---
> drivers/clk/rockchip/clk-rk3288.c | 2 +-
> include/dt-bindings/clock/rk3288-cru.h | 1 +
> 2 files changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/clk/rockchip/clk-rk3288.c
> b/drivers/clk/rockchip/clk-rk3288.c index 0df5bae..31c4f78 100644
> --- a/drivers/clk/rockchip/clk-rk3288.c
> +++ b/drivers/clk/rockchip/clk-rk3288.c
> @@ -647,7 +647,7 @@ static struct rockchip_clk_branch rk3288_clk_branches[]
> __initdata = { GATE(0, "pclk_efuse_1024", "pclk_cpu", 0,
> RK3288_CLKGATE_CON(11), 2, GFLAGS),
out of curiosity, as I haven't found anything about it yet, do you also know
what the pclk_efuse_1024 is used for?
Heiko
> GATE(PCLK_TZPC, "pclk_tzpc",
> "pclk_cpu", 0, RK3288_CLKGATE_CON(11), 3, GFLAGS), GATE(PCLK_UART2,
> "pclk_uart2", "pclk_cpu", 0, RK3288_CLKGATE_CON(11), 9, GFLAGS), - GATE(0,
> "pclk_efuse_256", "pclk_cpu", 0, RK3288_CLKGATE_CON(11), 10, GFLAGS),
> + GATE(PCLK_EFUSE256, "pclk_efuse_256", "pclk_cpu", 0,
> RK3288_CLKGATE_CON(11), 10, GFLAGS), GATE(PCLK_RKPWM, "pclk_rkpwm",
> "pclk_cpu", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(11), 11, GFLAGS),
>
> /* ddrctrl [DDR Controller PHY clock] gates */
> diff --git a/include/dt-bindings/clock/rk3288-cru.h
> b/include/dt-bindings/clock/rk3288-cru.h index c719aac..ab74d5e 100644
> --- a/include/dt-bindings/clock/rk3288-cru.h
> +++ b/include/dt-bindings/clock/rk3288-cru.h
> @@ -164,6 +164,7 @@
> #define PCLK_DDRUPCTL1 366
> #define PCLK_PUBL1 367
> #define PCLK_WDT 368
> +#define PCLK_EFUSE256 369
>
> /* hclk gates */
> #define HCLK_GPS 448
next prev parent reply other threads:[~2015-08-11 7:16 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-08-11 6:15 [PATCH v1 0/5] Add eFuse driver of Rockchip SoC Shunqian Zheng
2015-08-11 6:15 ` [PATCH v1 1/5] clk: rockchip: rk3288: Add the clock id of eFuse Shunqian Zheng
2015-08-11 6:15 ` Shunqian Zheng
2015-08-11 7:16 ` Heiko Stübner [this message]
2015-08-11 7:22 ` Heiko Stübner
2015-08-11 7:43 ` Shunqian Zheng
2015-08-11 7:43 ` Shunqian Zheng
2015-08-11 7:23 ` Shunqian Zheng
2015-08-11 6:15 ` [PATCH v1 2/5] nvmem: fix the out-of-range leak in read/write() Shunqian Zheng
2015-08-11 6:15 ` [PATCH v1 3/5] nvmem: rockchip-efuse: implement efuse driver Shunqian Zheng
2015-08-11 6:15 ` Shunqian Zheng
2015-08-11 8:13 ` Srinivas Kandagatla
2015-08-11 8:13 ` Srinivas Kandagatla
2015-08-11 6:15 ` [PATCH v1 4/5] Documentation: rockchip-efuse: describe the usage of eFuse Shunqian Zheng
2015-08-11 6:15 ` Shunqian Zheng
2015-08-11 6:15 ` [PATCH v1 5/5] ARM: dts: rockchip: add eFuse config of rk3288 SoC Shunqian Zheng
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