From: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
To: Geert Uytterhoeven <geert@linux-m68k.org>
Cc: Geert Uytterhoeven <geert+renesas@glider.be>,
Michael Turquette <mturquette@baylibre.com>,
Stephen Boyd <sboyd@codeaurora.org>,
linux-clk <linux-clk@vger.kernel.org>,
Linux-Renesas <linux-renesas-soc@vger.kernel.org>
Subject: Re: [PATCH 1/1] clk: renesas: cpg-mssr: r8a7796: add IMR clocks
Date: Tue, 21 Feb 2017 21:54:47 +0300 [thread overview]
Message-ID: <1b4f2247-d3cf-fcab-deaa-045db17a43bd@cogentembedded.com> (raw)
In-Reply-To: <CAMuHMdV1x2voYKnMKv8x3XvmGwBA8SgwkhJZcnkycypdPhVjzA@mail.gmail.com>
On 02/20/2017 11:38 AM, Geert Uytterhoeven wrote:
>> Add the IMR[0-1] clocks to the R8A7796 CPG/MSSR driver.
>>
>> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
>
> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
>
>> --- linux.orig/drivers/clk/renesas/r8a7796-cpg-mssr.c
>> +++ linux/drivers/clk/renesas/r8a7796-cpg-mssr.c
>> @@ -179,6 +179,8 @@ static const struct mssr_mod_clk r8a7796
>> DEF_MOD("vin1", 810, R8A7796_CLK_S0D2),
>> DEF_MOD("vin0", 811, R8A7796_CLK_S0D2),
>> DEF_MOD("etheravb", 812, R8A7796_CLK_S0D6),
>> + DEF_MOD("imr1", 822, R8A7796_CLK_S2D1),
>> + DEF_MOD("imr0", 823, R8A7796_CLK_S2D1),
>
> According to R-Car Gen3 Hardware Users Manual Rev.0.53E, the parent
> clock is S0D2, like on H3 ES2.0.
Not S0D4? I'd expect that what they call "register access" to be
controlled by the MSSR bits...
> Will queue in clk-renesas-for-v4.12 with corrected parent clock.
So, what have you used for 7795 and 7796?
> Gr{oetje,eeting}s,
>
> Geert
MBR, Sergei
next prev parent reply other threads:[~2017-02-21 18:54 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-02-18 21:39 [PATCH 1/1] clk: renesas: cpg-mssr: r8a7796: add IMR clocks Sergei Shtylyov
2017-02-18 21:39 ` Sergei Shtylyov
2017-02-20 8:38 ` Geert Uytterhoeven
2017-02-20 20:11 ` Sergei Shtylyov
2017-02-21 18:54 ` Sergei Shtylyov [this message]
2017-02-21 19:39 ` Geert Uytterhoeven
2017-02-21 19:49 ` Sergei Shtylyov
2017-02-28 20:09 ` Geert Uytterhoeven
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