Re: force wake reference counting (another try)

From: Chris Wilson <chris@chris-wilson.co.uk>
To: Keith Packard <keithp@keithp.com>, Ben Widawsky <ben@bwidawsk.net>
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: force wake reference counting (another try)
Date: Tue, 12 Apr 2011 18:21:23 +0100	[thread overview]
Message-ID: <1bdc18$k6n2j0@fmsmga002.fm.intel.com> (raw)
In-Reply-To: <yunr597pfx8.fsf@aiko.keithp.com>

On Tue, 12 Apr 2011 09:56:03 -0700, Keith Packard <keithp@keithp.com> wrote:
> On Tue, 12 Apr 2011 09:30:22 -0700, Ben Widawsky <ben@bwidawsk.net> wrote:
> 
> > I am going to spend at least a day tracking down, and hopefully fixing
> > warnings if you agree with my next statement that it is in fact a
> > problem. My hope is there aren't too many cases.
> 
> I can't see how we can survive without using exactly one lock covering
> the wake locks on SNB. Has someone tried sticking a simple spinlock
> around the whole sequence (force_wake_get, op, force_wake_put)?

Agreed. I had been working under the assumption that dev->struct_mutex was
the sufficient lock. This may be entirely due to the false premise that we
only needed i915_gt_read() for the ring registers. I still haven't looked
through just what registers are impacted.

Ben, as you work through this can you amend the register names to
include whether it is inside the GT power well? And a precise next to
gen6_gt_forcewake_get() on which groups of registers are affected.

GEN6_GT_x vs GEN6_y?
-Chris

-- 
Chris Wilson, Intel Open Source Technology Centre