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From: Sheng Yang <sheng@linux.intel.com>
To: Avi Kivity <avi@redhat.com>
Cc: kvm@vger.kernel.org, Marcelo Tosatti <mtosatti@redhat.com>,
	Joerg Roedel <joerg.roedel@amd.com>
Subject: Re: [PATCH 2/3] KVM: VMX: Simplify pdptr and cr3 management
Date: Tue, 2 Jun 2009 17:30:37 +0800	[thread overview]
Message-ID: <200906021730.38414.sheng@linux.intel.com> (raw)
In-Reply-To: <4A24F043.6070109@redhat.com>

On Tuesday 02 June 2009 17:26:27 Avi Kivity wrote:
> Sheng Yang wrote:
> > On Monday 01 June 2009 21:22:02 Avi Kivity wrote:
> >> Instead of reading the PDPTRs from memory after every exit (which is
> >> slow and wrong, as the PDPTRs are stored on the cpu), sync the PDPTRs
> >> from memory to the VMCS before entry, and from the VMCS to memory after
> >> exit. Do the same for cr3.
> >
> > Thanks for fixing!
> >
> > After review my original code, I found a potential bug. For SDM 3B have
> > this:
> >
> > 23.3.4 Saving Non-Register State
> > ...
> > If the logical processor supports the 1-setting of the “enable EPT” VM-
> > execution control, values are saved into the four (4) PDPTE fields as
> > follows: — If the “enable EPT” VM-execution control is 1 and the logical
> > processor was using PAE paging at the time of the VM exit, the PDPTE
> > values currently in use are saved:
> > • The values saved into bits 11:9 of each of the fields is undefined.
> > • If the value saved into one of the fields has bit 0 (present) clear,
> > the value saved into bits 63:1 of that field is undefined. That value
> > need not correspond to the value that was loaded by VM entry or to any
> > value that might have been loaded in VMX non-root operation.
> > • If the value saved into one of the fields has bit 0 (present) set, the
> > value saved into bits 63:12 of the field is a guest-physical address.
> > — If the “enable EPT” VM-execution control is 0 or the logical processor
> > was not using PAE paging at the time of the VM exit, the values saved are
> > undefined.
> >
> > But drop the ept_load_pdptrs() when exit and add it in cr0 handling
> > result in Windows PAE guest hang on boot. I am checking it now. Any
> > thoughts?...
>
> You mean with the new code?  What version of Windows exactly?
>
> I'll check it out, though EPTs are a little hard to find here.

No, no, not with the new code. For CPU can load pdptrs if EPT enabled with PAE 
from VM exit, there should not be necessary load it explicitly. So I estimate 
the ept_load_pdptr() in exit handler, and put it in CR0 handling. Just tried 
to optimize load-pdptr according to the spec, but not got the desired 
result...

So I am trying to find the failure reason...

-- 
regards
Yang, Sheng

  reply	other threads:[~2009-06-02  9:30 UTC|newest]

Thread overview: 17+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2009-06-01 13:22 [PATCH 0/3] Cache PDPTRs under ept/npt Avi Kivity
2009-06-01 13:22 ` [PATCH 1/3] KVM: VMX: Avoid duplicate ept tlb flush when setting cr3 Avi Kivity
2009-06-01 13:22 ` [PATCH 2/3] KVM: VMX: Simplify pdptr and cr3 management Avi Kivity
2009-06-02  9:22   ` Sheng Yang
2009-06-02  9:26     ` Avi Kivity
2009-06-02  9:30       ` Sheng Yang [this message]
2009-06-02  9:46         ` Avi Kivity
2009-06-02  9:56           ` Sheng Yang
2009-06-02 10:16             ` Avi Kivity
2009-06-02 11:31               ` Sheng Yang
2009-06-02 11:44                 ` Avi Kivity
2009-06-01 13:22 ` [PATCH 3/3] KVM: Cache pdptrs Avi Kivity
2009-06-02  9:04   ` Joerg Roedel
2009-06-02  9:09     ` Avi Kivity
2009-06-02  9:30       ` Joerg Roedel
2009-06-02  9:44         ` Avi Kivity
2009-06-02 11:50       ` Avi Kivity

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