From: "Ville Syrjälä" <ville.syrjala@linux.intel.com>
To: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Cc: dri-devel@lists.freedesktop.org
Subject: Re: [RFC/PATCH] drm: Add XRGB8626262 (RGB 6:6:6) pixel format
Date: Wed, 27 Mar 2013 13:06:20 +0200 [thread overview]
Message-ID: <20130327110620.GZ4469@intel.com> (raw)
In-Reply-To: <1364375969-5266-1-git-send-email-laurent.pinchart+renesas@ideasonboard.com>
On Wed, Mar 27, 2013 at 10:19:29AM +0100, Laurent Pinchart wrote:
> This format is an odd beast, implemented by Renesas R-Car hardware. It
> stores RGB 6:6:6 pixels in 32 bits as
>
> [31:0] x:R:x:G:x:B:x 8:6:2:6:2:6:2 little endian
>
> Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
> ---
>
> Hello,
>
> I came across this weird format on a Renesas SoC display controller. This is
> essentially XRGB8888 with the two low order bits of each component ignored by
> the hardware.
It sounds like it's no different than shoveling XRGB8888 down a 6bpc
pipe w/o dithering.
Could we just pretend it's XRGB8888, or can the low order bits have
some special meaning which would require treating them as special?
--
Ville Syrjälä
Intel OTC
next prev parent reply other threads:[~2013-03-27 11:06 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2013-03-27 9:19 [RFC/PATCH] drm: Add XRGB8626262 (RGB 6:6:6) pixel format Laurent Pinchart
2013-03-27 11:06 ` Ville Syrjälä [this message]
2013-03-27 14:09 ` Laurent Pinchart
2013-03-27 14:16 ` Ville Syrjälä
2013-03-27 14:21 ` Laurent Pinchart
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