Re: [PATCH v3 1/2] drm/i915/bxt: work around HW coherency issue when accessing GPU seqno

From: Chris Wilson <chris@chris-wilson.co.uk>
To: Imre Deak <imre.deak@intel.com>
Cc: Jani Nikula <jani.nikula@intel.com>,
	intel-gfx@lists.freedesktop.org,
	Mika Kuoppala <mika.kuoppala@intel.com>
Subject: Re: [PATCH v3 1/2] drm/i915/bxt: work around HW coherency issue when accessing GPU seqno
Date: Fri, 14 Aug 2015 17:21:14 +0100	[thread overview]
Message-ID: <20150814162113.GH27217@nuc-i3427.alporthouse.com> (raw)
In-Reply-To: <1439566527-28692-1-git-send-email-imre.deak@intel.com>

On Fri, Aug 14, 2015 at 06:35:27PM +0300, Imre Deak wrote:
> By running igt/store_dword_loop_render on BXT we can hit a coherency
> problem where the seqno written at GPU command completion time is not
> seen by the CPU. This results in __i915_wait_request seeing the stale
> seqno and not completing the request (not considering the lost
> interrupt/GPU reset mechanism). I also verified that this isn't a case
> of a lost interrupt, or that the command didn't complete somehow: when
> the coherency issue occured I read the seqno via an uncached GTT mapping
> too. While the cached version of the seqno still showed the stale value
> the one read via the uncached mapping was the correct one.
> 
> Work around this issue by clflushing the corresponding CPU cacheline
> following any store of the seqno and preceding any reading of it. When
> reading it do this only when the caller expects a coherent view.
> 
> v2:
> - fix using the proper logical && instead of a bitwise & (Jani, Mika)
> - limit the workaround to A stepping, on later steppings this HW issue
>   is fixed
> v3:
> - use a separate get_seqno/set_seqno vfunc (Chris)
> 
> Testcase: igt/store_dword_loop_render
> Signed-off-by: Imre Deak <imre.deak@intel.com>

I'm not going to quibble about the whitespace or the code duplication
that isn't your fault...

Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
-Chris

-- 
Chris Wilson, Intel Open Source Technology Centre
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