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From: "Ville Syrjälä" <ville.syrjala@linux.intel.com>
To: Jesse Barnes <jbarnes@virtuousgeek.org>
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH 30/43] drm/i915: Parametrize and fix SWF registers
Date: Mon, 12 Oct 2015 19:17:45 +0300	[thread overview]
Message-ID: <20151012161745.GI26517@intel.com> (raw)
In-Reply-To: <561BDAB5.5070600@virtuousgeek.org>

On Mon, Oct 12, 2015 at 09:07:17AM -0700, Jesse Barnes wrote:
> On 09/18/2015 10:03 AM, ville.syrjala@linux.intel.com wrote:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > 
> > Parametrize the SWF registers. This also fixes the register offsets,
> > which were mostly garbage in the old defines.
> > 
> > Also save/restore only as many SWF registers that each platform has.
> > 
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > ---
> >  drivers/gpu/drm/i915/i915_drv.h     |  2 +-
> >  drivers/gpu/drm/i915/i915_reg.h     | 28 +++++++++++------------
> >  drivers/gpu/drm/i915/i915_suspend.c | 45 ++++++++++++++++++++++++++++---------
> >  3 files changed, 50 insertions(+), 25 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> > index 3bf8a9b..3e35e08 100644
> > --- a/drivers/gpu/drm/i915/i915_drv.h
> > +++ b/drivers/gpu/drm/i915/i915_drv.h
> > @@ -1041,7 +1041,7 @@ struct i915_suspend_saved_registers {
> >  	u32 saveMI_ARB_STATE;
> >  	u32 saveSWF0[16];
> >  	u32 saveSWF1[16];
> > -	u32 saveSWF2[3];
> > +	u32 saveSWF3[3];
> >  	uint64_t saveFENCE[I915_MAX_NUM_FENCES];
> >  	u32 savePCH_PORT_HOTPLUG;
> >  	u16 saveGCDGMBUS;
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> > index 0cc41e4b..57b9469 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -4941,20 +4941,20 @@ enum skl_disp_power_wells {
> >  #define I915_LO_DISPBASE(val)	(val & ~DISP_BASEADDR_MASK)
> >  #define I915_HI_DISPBASE(val)	(val & DISP_BASEADDR_MASK)
> >  
> > -/* VBIOS flags */
> > -#define SWF00			(dev_priv->info.display_mmio_offset + 0x71410)
> > -#define SWF01			(dev_priv->info.display_mmio_offset + 0x71414)
> > -#define SWF02			(dev_priv->info.display_mmio_offset + 0x71418)
> > -#define SWF03			(dev_priv->info.display_mmio_offset + 0x7141c)
> > -#define SWF04			(dev_priv->info.display_mmio_offset + 0x71420)
> > -#define SWF05			(dev_priv->info.display_mmio_offset + 0x71424)
> > -#define SWF06			(dev_priv->info.display_mmio_offset + 0x71428)
> > -#define SWF10			(dev_priv->info.display_mmio_offset + 0x70410)
> > -#define SWF11			(dev_priv->info.display_mmio_offset + 0x70414)
> > -#define SWF14			(dev_priv->info.display_mmio_offset + 0x71420)
> > -#define SWF30			(dev_priv->info.display_mmio_offset + 0x72414)
> > -#define SWF31			(dev_priv->info.display_mmio_offset + 0x72418)
> > -#define SWF32			(dev_priv->info.display_mmio_offset + 0x7241c)
> > +/*
> > + * VBIOS flags
> > + * gen2:
> > + * [00:06] alm,mgm
> > + * [10:16] all
> > + * [30:32] alm,mgm
> > + * gen3+:
> > + * [00:0f] all
> > + * [10:1f] all
> > + * [30:32] all
> > + */
> > +#define SWF0(i)	(dev_priv->info.display_mmio_offset + 0x70410 + (i) * 4)
> > +#define SWF1(i)	(dev_priv->info.display_mmio_offset + 0x71410 + (i) * 4)
> > +#define SWF3(i)	(dev_priv->info.display_mmio_offset + 0x72414 + (i) * 4)
> >  
> >  /* Pipe B */
> >  #define _PIPEBDSL		(dev_priv->info.display_mmio_offset + 0x71000)
> > diff --git a/drivers/gpu/drm/i915/i915_suspend.c b/drivers/gpu/drm/i915/i915_suspend.c
> > index 1ccac61..2d91821 100644
> > --- a/drivers/gpu/drm/i915/i915_suspend.c
> > +++ b/drivers/gpu/drm/i915/i915_suspend.c
> > @@ -122,12 +122,24 @@ int i915_save_state(struct drm_device *dev)
> >  	dev_priv->regfile.saveMI_ARB_STATE = I915_READ(MI_ARB_STATE);
> >  
> >  	/* Scratch space */
> > -	for (i = 0; i < 16; i++) {
> > -		dev_priv->regfile.saveSWF0[i] = I915_READ(SWF00 + (i << 2));
> > -		dev_priv->regfile.saveSWF1[i] = I915_READ(SWF10 + (i << 2));
> > +	if (IS_GEN2(dev_priv) && IS_MOBILE(dev_priv)) {
> > +		for (i = 0; i < 7; i++) {
> > +			dev_priv->regfile.saveSWF0[i] = I915_READ(SWF0(i));
> > +			dev_priv->regfile.saveSWF1[i] = I915_READ(SWF1(i));
> > +		}
> > +		for (i = 0; i < 3; i++)
> > +			dev_priv->regfile.saveSWF3[i] = I915_READ(SWF3(i));
> > +	} else if (IS_GEN2(dev_priv)) {
> > +		for (i = 0; i < 7; i++)
> > +			dev_priv->regfile.saveSWF1[i] = I915_READ(SWF1(i));
> > +	} else if (HAS_GMCH_DISPLAY(dev_priv)) {
> > +		for (i = 0; i < 16; i++) {
> > +			dev_priv->regfile.saveSWF0[i] = I915_READ(SWF0(i));
> > +			dev_priv->regfile.saveSWF1[i] = I915_READ(SWF1(i));
> > +		}
> > +		for (i = 0; i < 3; i++)
> > +			dev_priv->regfile.saveSWF3[i] = I915_READ(SWF3(i));
> >  	}
> > -	for (i = 0; i < 3; i++)
> > -		dev_priv->regfile.saveSWF2[i] = I915_READ(SWF30 + (i << 2));
> >  
> >  	mutex_unlock(&dev->struct_mutex);
> >  
> > @@ -156,12 +168,25 @@ int i915_restore_state(struct drm_device *dev)
> >  	/* Memory arbitration state */
> >  	I915_WRITE(MI_ARB_STATE, dev_priv->regfile.saveMI_ARB_STATE | 0xffff0000);
> >  
> > -	for (i = 0; i < 16; i++) {
> > -		I915_WRITE(SWF00 + (i << 2), dev_priv->regfile.saveSWF0[i]);
> > -		I915_WRITE(SWF10 + (i << 2), dev_priv->regfile.saveSWF1[i]);
> > +	/* Scratch space */
> > +	if (IS_GEN2(dev_priv) && IS_MOBILE(dev_priv)) {
> > +		for (i = 0; i < 7; i++) {
> > +			I915_WRITE(SWF0(i), dev_priv->regfile.saveSWF0[i]);
> > +			I915_WRITE(SWF1(i), dev_priv->regfile.saveSWF1[i]);
> > +		}
> > +		for (i = 0; i < 3; i++)
> > +			I915_WRITE(SWF3(i), dev_priv->regfile.saveSWF3[i]);
> > +	} else if (IS_GEN2(dev_priv)) {
> > +		for (i = 0; i < 7; i++)
> > +			I915_WRITE(SWF1(i), dev_priv->regfile.saveSWF1[i]);
> > +	} else if (HAS_GMCH_DISPLAY(dev_priv)) {
> > +		for (i = 0; i < 16; i++) {
> > +			I915_WRITE(SWF0(i), dev_priv->regfile.saveSWF0[i]);
> > +			I915_WRITE(SWF1(i), dev_priv->regfile.saveSWF1[i]);
> > +		}
> > +		for (i = 0; i < 3; i++)
> > +			I915_WRITE(SWF3(i), dev_priv->regfile.saveSWF3[i]);
> >  	}
> > -	for (i = 0; i < 3; i++)
> > -		I915_WRITE(SWF30 + (i << 2), dev_priv->regfile.saveSWF2[i]);
> >  
> >  	mutex_unlock(&dev->struct_mutex);
> >  
> > 
> 
> I think these were added speculatively in the first place.  Maybe we'd
> see a bug on 8xx without these saved & restored, but I wonder if we'd
> see anything else?

It's hard to know what the firmware does with these. IIRC there's a
"driver loaded" bit in there somewhere we perhaps should set to tell
the firmware to stay away.

Oh and I did eventually find the SWF registers for PCH platforms too.
Currently we don't save/restore those at all, so not sure we should
start either.

> 
> Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>

-- 
Ville Syrjälä
Intel OTC
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

  reply	other threads:[~2015-10-12 16:20 UTC|newest]

Thread overview: 136+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2015-09-18 17:03 [PATCH 00/43] drm/i915: Type safe register read/write and a ton of prep work ville.syrjala
2015-09-18 17:03 ` [PATCH 01/43] drm/i915: Don't pass sdvo_reg to intel_sdvo_select_{ddc, i2c}_bus() ville.syrjala
2015-09-21  7:34   ` Jani Nikula
2015-09-18 17:03 ` [PATCH 02/43] drm/i915: Parametrize LRC registers ville.syrjala
2015-09-21  7:36   ` Jani Nikula
2015-09-18 17:03 ` [PATCH 03/43] drm/i915: Parametrize GEN7_GT_SCRATCH and GEN7_LRA_LIMITS ville.syrjala
2015-09-21  7:37   ` Jani Nikula
2015-09-18 17:03 ` [PATCH 04/43] drm/i915: Parametrize fence registers ville.syrjala
2015-09-21  7:45   ` Jani Nikula
2015-09-21 12:33     ` Ville Syrjälä
2015-09-21 13:07       ` Ville Syrjälä
2015-09-21 15:05   ` [PATCH v2 " ville.syrjala
2015-09-25 12:02     ` Jani Nikula
2015-09-28  8:31       ` Daniel Vetter
2015-09-18 17:03 ` [PATCH 05/43] drm/i915: Parametrize FBC_TAG registers ville.syrjala
2015-09-21  7:46   ` Jani Nikula
2015-09-18 17:03 ` [PATCH 06/43] drm/i915: Parametrize ILK turbo registers ville.syrjala
2015-09-21  7:47   ` Jani Nikula
2015-09-18 17:03 ` [PATCH 07/43] drm/i915: Replace raw numbers with the approproate register name in ILK turbo code ville.syrjala
2015-09-21  7:48   ` Jani Nikula
2015-09-18 17:03 ` [PATCH 08/43] drm/i915: Parametrize TV luma/chroma filter registers ville.syrjala
2015-09-21  7:50   ` Jani Nikula
2015-09-18 17:03 ` [PATCH 09/43] drm/i915: Parametrize DDI_BUF_TRANS registers ville.syrjala
2015-09-21  7:59   ` Jani Nikula
2015-09-18 17:03 ` [PATCH 10/43] drm/i915: Parametrize CSR_PROGRAM registers ville.syrjala
2015-09-23 14:15   ` Mika Kuoppala
2015-09-23 15:17     ` Daniel Vetter
2015-09-18 17:03 ` [PATCH 11/43] drm/i915: Parametrize UOS_RSA_SCRATCH ville.syrjala
2015-09-28 11:39   ` Jani Nikula
2015-09-18 17:03 ` [PATCH 12/43] drm/i915: Add LO/HI PRIVATE_PAT registers ville.syrjala
2015-09-28 11:40   ` Jani Nikula
2015-09-18 17:03 ` [PATCH 13/43] drm/i915: Always use GEN8_RING_PDP_{LDW, UDW} instead of hand rolling the register offsets ville.syrjala
2015-09-28 11:42   ` Jani Nikula
2015-09-18 17:03 ` [PATCH 14/43] drm/i915: Include MCHBAR_MIRROR_BASE in ILK_GDSR ville.syrjala
2015-09-28 11:44   ` Jani Nikula
2015-09-18 17:03 ` [PATCH 15/43] drm/i915: Parametrize PALETTE and LGC_PALETTE ville.syrjala
2015-09-28 11:45   ` Jani Nikula
2015-09-18 17:03 ` [PATCH 16/43] drm/i915: s/_CURACNTR/CURCNTR(PIPE_A)/ ville.syrjala
2015-09-22 16:47   ` [PATCH v2 " ville.syrjala
2015-09-28 11:50     ` Jani Nikula
2015-09-28 13:35       ` Daniel Vetter
2015-09-28 11:49   ` [PATCH " Jani Nikula
2015-09-18 17:03 ` [PATCH 17/43] drm/i915: s/_FDI_RXA_.../FDI_RX_...(PIPE_A)/ ville.syrjala
2015-09-29 14:14   ` Jani Nikula
2015-09-18 17:03 ` [PATCH 18/43] drm/i915: s/_TRANSA_CHICKEN/TRANS_CHICKEN(PIPE_A)/ ville.syrjala
2015-09-29 14:16   ` Jani Nikula
2015-09-18 17:03 ` [PATCH 19/43] drm/i915: s/GET_CFG_CR1_REG/DPLL_CFGCR1/ etc ville.syrjala
2015-09-30 13:44   ` Jani Nikula
2015-09-30 13:53     ` Ville Syrjälä
2015-09-30 14:06   ` [PATCH v2 " ville.syrjala
2015-09-18 17:03 ` [PATCH 20/43] drm/i915: Use paramtrized WRPLL_CTL() ville.syrjala
2015-09-30 13:58   ` Jani Nikula
2015-09-30 14:00     ` Ville Syrjälä
2015-10-26 14:49     ` Ville Syrjälä
2015-09-18 17:03 ` [PATCH 21/43] drm/i915: Add VLV_HDMIB etc. which already include VLV_DISPLAY_BASE ville.syrjala
2015-09-28 11:53   ` Jani Nikula
2015-09-18 17:03 ` [PATCH 22/43] drm/i915: s/DDI_BUF_CTL_A/DDI_BUF_CTL(PORT_A)/ ville.syrjala
2015-09-28 11:53   ` Jani Nikula
2015-09-28 13:38     ` Daniel Vetter
2015-09-18 17:03 ` [PATCH 23/43] drm/i915: Eliminate weird parameter inversion from BXT PPS registers ville.syrjala
2015-10-12 16:41   ` [PATCH v2 " ville.syrjala
2015-09-18 17:03 ` [PATCH 24/43] drm/i915: Parametrize HSW video DIP data registers ville.syrjala
2015-10-12 15:54   ` Jesse Barnes
2015-10-12 16:15     ` Ville Syrjälä
2015-09-18 17:03 ` [PATCH 25/43] drm/i915: Include gpio_mmio_base in GMBUS reg defines ville.syrjala
2015-10-12 15:56   ` Jesse Barnes
2015-09-18 17:03 ` [PATCH 26/43] drm/i915: Protect register macro arguments ville.syrjala
2015-10-12 16:03   ` Jesse Barnes
2015-09-18 17:03 ` [PATCH 27/43] drm/i915: Fix a few bad hex numbers in register defines ville.syrjala
2015-10-12 16:04   ` Jesse Barnes
2015-09-18 17:03 ` [PATCH 28/43] drm/i915: Turn GEN5_ASSERT_IIR_IS_ZERO() into a function ville.syrjala
2015-10-12 16:05   ` Jesse Barnes
2015-09-18 17:03 ` [PATCH 29/43] drm/i915: s/PIPE_FRMCOUNT_GM45/PIPE_FRMCOUNT_G4X/ etc ville.syrjala
2015-10-12 16:06   ` Jesse Barnes
2015-09-18 17:03 ` [PATCH 30/43] drm/i915: Parametrize and fix SWF registers ville.syrjala
2015-10-12 16:07   ` Jesse Barnes
2015-10-12 16:17     ` Ville Syrjälä [this message]
2015-09-18 17:03 ` [PATCH 31/43] drm/i915: Throw out some useless variables ville.syrjala
2015-09-22 16:50   ` [PATCH v2 " ville.syrjala
2015-10-12 16:09     ` Jesse Barnes
2015-09-18 17:03 ` [PATCH 32/43] drm/i915: Clean up LVDS register handling ville.syrjala
2015-10-12 16:09   ` Jesse Barnes
2015-11-01 15:33   ` Lukas Wunner
2015-11-04 16:59     ` Ville Syrjälä
2015-09-18 17:03 ` [PATCH 33/43] drm/i915: Remove dev_priv argument from NEEDS_FORCE_WAKE ville.syrjala
2015-10-12 16:12   ` Jesse Barnes
2015-10-13 11:21     ` Daniel Vetter
2015-09-18 17:03 ` [PATCH 34/43] drm/i915: Turn __raw_i915_read8() & co. in to inline functions ville.syrjala
2015-09-18 17:03 ` [PATCH 35/43] drm/i915: Move __raw_i915_read8() & co. into i915_drv.h ville.syrjala
2015-09-18 17:42   ` Chris Wilson
2015-09-18 18:23     ` Ville Syrjälä
2015-09-18 18:33       ` Chris Wilson
2015-09-18 18:37         ` Ville Syrjälä
2015-09-18 18:44           ` Chris Wilson
2015-09-18 19:26             ` Ville Syrjälä
2015-09-21 16:26               ` Jesse Barnes
2015-09-21 16:53                 ` Ville Syrjälä
2015-09-21 16:57                   ` Jesse Barnes
2015-09-18 17:03 ` [PATCH 36/43] drm/i915: Remove the magic AUX_CTL is at DP + foo tricks ville.syrjala
2015-09-18 17:03 ` [PATCH 37/43] drm/i915: Replace the aux ddc name switch statement with a table ville.syrjala
2015-09-18 17:03 ` [PATCH 38/43] drm/i915: Parametrize AUX registes ville.syrjala
2015-09-28 12:15   ` Jani Nikula
2015-09-28 13:28     ` Daniel Vetter
2015-09-28 13:34       ` Ville Syrjälä
2015-09-28 13:52         ` Daniel Vetter
2015-09-28 13:57           ` Jani Nikula
2015-09-28 15:09   ` [PATCH v2 38/43] drm/i915: Parametrize AUX registers ville.syrjala
2015-10-20 13:05     ` Jani Nikula
2015-10-20 13:37       ` Ville Syrjälä
2015-10-20 14:00     ` [PATCH v3 " ville.syrjala
2015-10-21  7:08       ` Jani Nikula
2015-09-18 17:03 ` [PATCH 39/43] drm/i915: Add dev_priv->psr_mmio_base ville.syrjala
2015-10-20 13:08   ` Jani Nikula
2015-10-20 14:01   ` [PATCH v2 " ville.syrjala
2015-10-21  7:09     ` Jani Nikula
2015-09-18 17:03 ` [PATCH 40/43] drm/i915: Store aux data reg offsets in intel_dp->aux_ch_data_reg[] ville.syrjala
2015-09-28 12:28   ` Jani Nikula
2015-09-28 14:36     ` Ville Syrjälä
2015-09-28 15:10   ` [PATCH v2 " ville.syrjala
2015-10-20 14:02     ` [PATCH v3 " ville.syrjala
2015-09-18 17:03 ` [PATCH 41/43] drm/i915: Model PSR AUX register selection more like the normal AUX code ville.syrjala
2015-09-28 15:11   ` [PATCH v2 " ville.syrjala
2015-09-18 17:03 ` [PATCH 42/43] drm/i915: Prefix raw register defines with underscore ville.syrjala
2015-09-18 17:03 ` [RFC][PATCH 43/43] WIP: drm/i915: Type safe register read/write ville.syrjala
2015-09-18 17:33   ` Chris Wilson
2015-09-18 17:43     ` Ville Syrjälä
2015-09-18 18:12       ` Chris Wilson
2015-09-18 18:34         ` Ville Syrjälä
2015-09-23 15:23   ` Daniel Vetter
2015-09-24 15:38     ` Ville Syrjälä
2015-09-28 12:56       ` Jani Nikula
2015-09-28 13:03         ` Ville Syrjälä
2015-09-28 13:52           ` Daniel Vetter
2015-09-18 18:17 ` [PATCH 00/43] drm/i915: Type safe register read/write and a ton of prep work Chris Wilson
2015-09-22 17:41 ` Ville Syrjälä
2015-10-28 12:55 ` Jani Nikula

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