From: "Ville Syrjälä" <ville.syrjala@linux.intel.com>
To: Imre Deak <imre.deak@intel.com>
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH 2/4] drm/i915: Clean up L3 SQC register field definitions
Date: Tue, 26 Apr 2016 19:55:01 +0300 [thread overview]
Message-ID: <20160426165501.GZ4329@intel.com> (raw)
In-Reply-To: <1461587888-5047-2-git-send-email-imre.deak@intel.com>
On Mon, Apr 25, 2016 at 03:38:06PM +0300, Imre Deak wrote:
> No need for hard-coding the register value, the corresponding fields are
> defined properly in BSpec.
>
> No functional change.
>
> Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/i915_reg.h | 3 ++-
> drivers/gpu/drm/i915/intel_pm.c | 3 ++-
> 2 files changed, 4 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index c21b71c..0cb2e17 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -6073,7 +6073,8 @@ enum skl_disp_power_wells {
> #define VLV_B0_WA_L3SQCREG1_VALUE 0x00D30000
>
> #define GEN8_L3SQCREG1 _MMIO(0xB100)
> -#define BDW_WA_L3SQCREG1_DEFAULT 0x784000
> +#define L3_GENERAL_PRIO_CREDITS(x) (((x) >> 1) << 19)
> +#define L3_HIGH_PRIO_CREDITS(x) (((x) >> 1) << 14)
>
> #define GEN7_L3CNTLREG1 _MMIO(0xB01C)
> #define GEN7_WA_FOR_GEN7_L3_CONTROL 0x3C47FF8C
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index a6fd4dd..a9b7626 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -6710,7 +6710,8 @@ static void broadwell_init_clock_gating(struct drm_device *dev)
> */
> misccpctl = I915_READ(GEN7_MISCCPCTL);
> I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
> - I915_WRITE(GEN8_L3SQCREG1, BDW_WA_L3SQCREG1_DEFAULT);
> + I915_WRITE(GEN8_L3SQCREG1, L3_GENERAL_PRIO_CREDITS(30) |
> + L3_HIGH_PRIO_CREDITS(2));
> /*
> * Wait at least 100 clocks before re-enabling clock gating. See
> * the definition of L3SQCREG1 in BSpec.
> --
> 2.5.0
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Ville Syrjälä
Intel OTC
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Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
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next prev parent reply other threads:[~2016-04-26 16:55 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-04-25 12:38 [PATCH 1/4] drm/i915/bdw: Add missing delay during L3 SQC credit programming Imre Deak
2016-04-25 12:38 ` [PATCH 2/4] drm/i915: Clean up L3 SQC register field definitions Imre Deak
2016-04-26 8:11 ` Mika Kuoppala
2016-04-26 9:03 ` Imre Deak
2016-04-26 9:21 ` Imre Deak
2016-04-26 16:55 ` Ville Syrjälä [this message]
2016-04-25 12:38 ` [PATCH 3/4] drm/i915/chv: Tune L3 SQC credits based on actual latencies Imre Deak
2016-04-25 13:16 ` Ville Syrjälä
2016-04-26 16:19 ` Ville Syrjälä
2016-04-26 16:39 ` [PATCH v2 " Imre Deak
2016-04-26 16:51 ` Ville Syrjälä
2016-04-25 12:38 ` [PATCH 4/4] drm/i915/bxt: " Imre Deak
2016-04-26 16:41 ` [PATCH v2 " Imre Deak
2016-04-26 16:53 ` Ville Syrjälä
2016-04-25 14:03 ` ✗ Fi.CI.BAT: failure for series starting with [1/4] drm/i915/bdw: Add missing delay during L3 SQC credit programming Patchwork
2016-04-26 16:55 ` [PATCH 1/4] " Ville Syrjälä
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