Re: [PATCH 02/15] drm/i915/glk: Introduce Geminilake platform definition

From: Matt Roper <matthew.d.roper@intel.com>
To: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com>
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH 02/15] drm/i915/glk: Introduce Geminilake platform definition
Date: Thu, 10 Nov 2016 15:18:08 -0800	[thread overview]
Message-ID: <20161110231808.GW6536@intel.com> (raw)
In-Reply-To: <1478791400-21756-3-git-send-email-ander.conselvan.de.oliveira@intel.com>

On Thu, Nov 10, 2016 at 05:23:07PM +0200, Ander Conselvan de Oliveira wrote:
> Geminilake is an Intel® Processor containing Intel® HD Graphics
> following Broxton.
> 
> Let's start by adding the platform definition. PCI IDs and plaform
> specific code will follow.
> 
> v2: Rebase (don't allow dev to be used with the new macro).
> Signed-off-by: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_drv.h | 2 ++
>  drivers/gpu/drm/i915/i915_pci.c | 6 ++++++
>  2 files changed, 8 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 4735b417..8a99e6e 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -667,6 +667,7 @@ struct intel_csr {
>  	func(is_broadwell); \
>  	func(is_skylake); \
>  	func(is_broxton); \
> +	func(is_geminilake); \
>  	func(is_kabylake); \
>  	func(is_preliminary); \
>  	/* Keep has_* in alphabetical order */ \
> @@ -2756,6 +2757,7 @@ struct drm_i915_cmd_table {
>  #define IS_BROADWELL(dev_priv)	((dev_priv)->info.is_broadwell)
>  #define IS_SKYLAKE(dev_priv)	((dev_priv)->info.is_skylake)
>  #define IS_BROXTON(dev_priv)	((dev_priv)->info.is_broxton)
> +#define IS_GEMINILAKE(dev_priv)	((dev_priv)->info.is_geminilake)
>  #define IS_KABYLAKE(dev_priv)	((dev_priv)->info.is_kabylake)
>  #define IS_MOBILE(dev_priv)	((dev_priv)->info.is_mobile)
>  #define IS_HSW_EARLY_SDV(dev_priv) (IS_HASWELL(dev_priv) && \
> diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
> index b8cdda1..dc2ba3f 100644
> --- a/drivers/gpu/drm/i915/i915_pci.c
> +++ b/drivers/gpu/drm/i915/i915_pci.c
> @@ -372,6 +372,12 @@ static const struct intel_device_info intel_broxton_info = {
>  	GEN9_LP_FEATURES,
>  };
>  
> +static const struct intel_device_info intel_geminilake_info = {
> +	.is_preliminary = 1,
> +	.is_geminilake = 1,
> +	GEN9_LP_FEATURES,

Just a drive-by comment, but I think you need to update the .ddb_size
from GEN9_LP_FEATURES as well.  Leaving BXT's value here is "safe" but
will make it very difficult to actually enable the additional planes
this platform has without exceeding the watermark limits.

Matt

> +};
> +
>  static const struct intel_device_info intel_kabylake_info = {
>  	BDW_FEATURES,
>  	.is_kabylake = 1,
> -- 
> 2.5.5
> 
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-- 
Matt Roper
Graphics Software Engineer
IoTG Platform Enabling & Development
Intel Corporation
(916) 356-2795
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