Re: [PATCH] drm/i915/bxt: Use smaller 8/3X MIPI clock divider value for dual link.

From: Bob Paauwe <bob.j.paauwe@intel.com>
To: David Weinehall <tao@kernel.org>
Cc: intel-gfx <intel-gfx@lists.freedesktop.org>
Subject: Re: [PATCH] drm/i915/bxt: Use smaller 8/3X MIPI clock divider value for dual link.
Date: Mon, 21 Nov 2016 10:06:56 -0800	[thread overview]
Message-ID: <20161121100656.01c0c2ec@bpaauwe-desk.fm.intel.com> (raw)
In-Reply-To: <20161119102056.GJ8202@suiko.acc.umu.se>

On Sat, 19 Nov 2016 11:20:56 +0100
David Weinehall <tao@kernel.org> wrote:

> On Fri, Nov 18, 2016 at 02:11:56PM -0800, Bob Paauwe wrote:
> > For a single link (channel) DSI panel we want to use a larger divider
> > and keep the clock rate down to save power when in DPI/video mode. However
> > when using a dual-link DSI panel this may reduce the clock below what's
> > needed to get a stable display.
> > 
> > Use the smaller divider (faster clock) for either DBI/command mode or
> > when using dual link.
> > 
> > Signed-off-by: Bob Paauwe <bob.j.paauwe@intel.com>
> > ---
> >  drivers/gpu/drm/i915/intel_dsi_pll.c | 9 +++++++--
> >  1 file changed, 7 insertions(+), 2 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/intel_dsi_pll.c b/drivers/gpu/drm/i915/intel_dsi_pll.c
> > index 56eff60..9edc57e 100644
> > --- a/drivers/gpu/drm/i915/intel_dsi_pll.c
> > +++ b/drivers/gpu/drm/i915/intel_dsi_pll.c
> > @@ -414,8 +414,13 @@ static void bxt_dsi_program_clocks(struct drm_device *dev, enum port port,
> >  	rx_div_lower = rx_div & RX_DIVIDER_BIT_1_2;
> >  	rx_div_upper = (rx_div & RX_DIVIDER_BIT_3_4) >> 2;
> >  
> > -	/* As per bpsec program the 8/3X clock divider to the below value */
> > -	if (dev_priv->vbt.dsi.config->is_cmd_mode)
> > +	/*
> > +	 * Set the 8/3X clock to divide by 3 for DBI mode as it needs a  
> 
> Shouldn't this be "divide by 2", to be consistent with the code
> and the commit message?

The value programmed into the bits isn't the same as the what the value
represents.  In this case we program the bits to 10b to use the by 3
divider and 11b to use the by 4 divider. 

It can also be programmed with 01b for a by 2 divider but that's not
used.

The 0x2 and 0x3 would probably be better represented by defines to
make that clear, but I'd think would be a separate patch.

> 
> > +	 * faster clock than DPI mode. However, dual link panels also
> > +	 * need the faster clock, even when in DPI mode.
> > +	 */
> > +	if (dev_priv->vbt.dsi.config->is_cmd_mode ||
> > +	    dev_priv->vbt.dsi.config->dual_link)
> >  		mipi_8by3_divider = 0x2;
> >  	else
> >  		mipi_8by3_divider = 0x3;  
> 
> 
> Kind regards, David Weinehall

-- 
--
Bob Paauwe                  
Bob.J.Paauwe@intel.com
IOTG / PED Software Organization
Intel Corp.  Folsom, CA
(916) 356-6193    

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