Re: [PATCH 8/8] drm/i915/get_params: Add HuC status to getparams

From: Chris Wilson <chris@chris-wilson.co.uk>
To: Arkadiusz Hiler <arkadiusz.hiler@intel.com>
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH 8/8] drm/i915/get_params: Add HuC status to getparams
Date: Fri, 16 Dec 2016 16:30:51 +0000	[thread overview]
Message-ID: <20161216163051.GA29871@nuc-i3427.alporthouse.com> (raw)
In-Reply-To: <20161216162138.GE2257@ahiler-desk.igk.intel.com>

On Fri, Dec 16, 2016 at 05:21:38PM +0100, Arkadiusz Hiler wrote:
> On Fri, Dec 16, 2016 at 04:12:36PM +0000, Chris Wilson wrote:
> > On Fri, Dec 16, 2016 at 03:43:46PM +0100, Arkadiusz Hiler wrote:
> > > On Thu, Dec 15, 2016 at 10:42:53PM +0000, Chris Wilson wrote:
> > > > On Thu, Dec 15, 2016 at 02:29:50PM -0800, anushasr wrote:
> > > > > From: Peter Antoine <peter.antoine@intel.com>
> > > > > 
> > > > > This patch will allow for getparams to return the status of the HuC.
> > > > > As the HuC has to be validated by the GuC this patch uses the validated
> > > > > status to show when the HuC is loaded and ready for use. You cannot use
> > > > > the loaded status as with the GuC as the HuC is verified after it is
> > > > > loaded and is not usable until it is verified.
> > > > > 
> > > > > v2: removed the forewakes as the registers are already force-woken.
> > > > >      (T.Ursulin)
> > > > > v4: rebased.
> > > > > v5: rebased on top of drm-tip.
> > > > > v6: rebased. Removed any reference to intel_huc.h
> > > > > v7: rebased. Rename I915_PARAM_HAS_HUC to I915_PARAM_HUC_STATUS.
> > > > > Remove intel_is_huc_valid() since it is used only in one place.
> > > > > Put the case of I915_PARAM_HAS_HUC() in the right place.
> > > > > 
> > > > > Signed-off-by: Peter Antoine <peter.antoine@intel.com>
> > > > > Reviewed-by: Arkadiusz Hiler <arkadiusz.hiler@intel.com>
> > > > > ---
> > > > >  drivers/gpu/drm/i915/i915_drv.c         | 4 ++++
> > > > >  drivers/gpu/drm/i915/intel_huc_loader.c | 1 -
> > > > >  include/uapi/drm/i915_drm.h             | 1 +
> > > > >  3 files changed, 5 insertions(+), 1 deletion(-)
> > > > > 
> > > > > diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
> > > > > index 85a47c2..0bc016d 100644
> > > > > --- a/drivers/gpu/drm/i915/i915_drv.c
> > > > > +++ b/drivers/gpu/drm/i915/i915_drv.c
> > > > > @@ -49,6 +49,7 @@
> > > > >  #include "i915_trace.h"
> > > > >  #include "i915_vgpu.h"
> > > > >  #include "intel_drv.h"
> > > > > +#include "intel_uc.h"
> > > > >  
> > > > >  static struct drm_driver driver;
> > > > >  
> > > > > @@ -315,6 +316,9 @@ static int i915_getparam(struct drm_device *dev, void *data,
> > > > >  	case I915_PARAM_MIN_EU_IN_POOL:
> > > > >  		value = INTEL_INFO(dev_priv)->sseu.min_eu_in_pool;
> > > > >  		break;
> > > > > +	case I915_PARAM_HUC_STATUS:
> > > > > +		value = I915_READ(HUC_STATUS2) & HUC_FW_VERIFIED;
> > > > 
> > > > Same question as last time: does the device need to be awake? We know is
> > > > one of the GT power wells, so presumably we need an rpm_get/rpm_put as
> > > > well to access the register.
> > > > -Chris
> > > 
> > > I get:
> > > 
> > > [ 1588.570174] [drm:i915_huc_load_status_info [i915]] HUC_STATUS2 PRE  24704
> > > [ 1588.571285] [drm:intel_runtime_suspend [i915]] Suspending device
> > > [ 1588.575768] [drm:intel_runtime_suspend [i915]] Device suspended
> > > [ 1588.577156] [drm:i915_huc_load_status_info [i915]] HUC_STATUS2 POST 24704
> > > [ 1588.578259] [drm:intel_runtime_resume [i915]] Resuming device
> > > 
> > > consistently from:
> > > 
> > > value = I915_READ(HUC_STATUS2);
> > > DRM_DEBUG_DRIVER("HUC_STATUS2 PRE  %d\n", value);
> > > i915_pm_ops.runtime_suspend(dev_priv->drm.dev);
> > > 
> > > value = I915_READ(HUC_STATUS2);
> > > DRM_DEBUG_DRIVER("HUC_STATUS2 POST %d\n", value);
> > > i915_pm_ops.runtime_resume(dev_priv->drm.dev);
> > 
> > Also do the test with i915.mmio_debug=9999
> > -Chris
> 
> Same effect. Works.

Ok, then just mark up that we don't need rpm here so that we don't freak
out in future scans for mmio access outside of rpm.
-Chris

-- 
Chris Wilson, Intel Open Source Technology Centre
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