From: Richard Henderson <rth@twiddle.net>
To: qemu-devel@nongnu.org
Cc: shorne@gmail.com
Subject: [Qemu-devel] [PATCH 05/22] target/openrisc: Implement lwa, swa
Date: Wed, 8 Feb 2017 20:51:37 -0800 [thread overview]
Message-ID: <20170209045154.16868-6-rth@twiddle.net> (raw)
In-Reply-To: <20170209045154.16868-1-rth@twiddle.net>
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
target/openrisc/cpu.c | 1 +
target/openrisc/cpu.h | 3 ++
target/openrisc/interrupt.c | 1 +
target/openrisc/interrupt_helper.c | 1 +
target/openrisc/machine.c | 24 ++++++++++------
target/openrisc/mmu.c | 1 +
target/openrisc/translate.c | 58 ++++++++++++++++++++++++++++++++++++++
7 files changed, 81 insertions(+), 8 deletions(-)
diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c
index 422139d..7fd2b9a 100644
--- a/target/openrisc/cpu.c
+++ b/target/openrisc/cpu.c
@@ -48,6 +48,7 @@ static void openrisc_cpu_reset(CPUState *s)
cpu->env.pc = 0x100;
cpu->env.sr = SR_FO | SR_SM;
+ cpu->env.lock_addr = -1;
s->exception_index = -1;
cpu->env.upr = UPR_UP | UPR_DMP | UPR_IMP | UPR_PICP | UPR_TTP;
diff --git a/target/openrisc/cpu.h b/target/openrisc/cpu.h
index 231c163..06d0e89 100644
--- a/target/openrisc/cpu.h
+++ b/target/openrisc/cpu.h
@@ -296,6 +296,9 @@ typedef struct CPUOpenRISCState {
uint32_t fpcsr; /* Float register */
float_status fp_status;
+ target_ulong lock_addr;
+ target_ulong lock_value;
+
uint32_t flags; /* cpu_flags, we only use it for exception
in solt so far. */
uint32_t btaken; /* the SR_F bit */
diff --git a/target/openrisc/interrupt.c b/target/openrisc/interrupt.c
index a243eb2..a981638 100644
--- a/target/openrisc/interrupt.c
+++ b/target/openrisc/interrupt.c
@@ -62,6 +62,7 @@ void openrisc_cpu_do_interrupt(CPUState *cs)
env->sr &= ~SR_TEE;
env->tlb->cpu_openrisc_map_address_data = &cpu_openrisc_get_phys_nommu;
env->tlb->cpu_openrisc_map_address_code = &cpu_openrisc_get_phys_nommu;
+ env->lock_addr = -1;
if (cs->exception_index > 0 && cs->exception_index < EXCP_NR) {
env->pc = (cs->exception_index << 8);
diff --git a/target/openrisc/interrupt_helper.c b/target/openrisc/interrupt_helper.c
index 0ed5146..a6d4df3 100644
--- a/target/openrisc/interrupt_helper.c
+++ b/target/openrisc/interrupt_helper.c
@@ -34,6 +34,7 @@ void HELPER(rfe)(CPUOpenRISCState *env)
cpu->env.pc = cpu->env.epcr;
cpu->env.npc = cpu->env.epcr;
cpu->env.sr = cpu->env.esr;
+ cpu->env.lock_addr = -1;
#ifndef CONFIG_USER_ONLY
if (cpu->env.sr & SR_DME) {
diff --git a/target/openrisc/machine.c b/target/openrisc/machine.c
index 17b0c77..d0b47ef 100644
--- a/target/openrisc/machine.c
+++ b/target/openrisc/machine.c
@@ -26,18 +26,26 @@
static const VMStateDescription vmstate_env = {
.name = "env",
- .version_id = 1,
- .minimum_version_id = 1,
+ .version_id = 2,
+ .minimum_version_id = 2,
.fields = (VMStateField[]) {
- VMSTATE_UINT32_ARRAY(gpr, CPUOpenRISCState, 32),
+ VMSTATE_UINTTL_ARRAY(gpr, CPUOpenRISCState, 32),
+ VMSTATE_UINTTL(pc, CPUOpenRISCState),
+ VMSTATE_UINTTL(npc, CPUOpenRISCState),
+ VMSTATE_UINTTL(ppc, CPUOpenRISCState),
+ VMSTATE_UINTTL(jmp_pc, CPUOpenRISCState),
+ VMSTATE_UINTTL(lock_addr, CPUOpenRISCState),
+ VMSTATE_UINTTL(lock_value, CPUOpenRISCState),
+ VMSTATE_UINTTL(epcr, CPUOpenRISCState),
+ VMSTATE_UINTTL(eear, CPUOpenRISCState),
VMSTATE_UINT32(sr, CPUOpenRISCState),
- VMSTATE_UINT32(epcr, CPUOpenRISCState),
- VMSTATE_UINT32(eear, CPUOpenRISCState),
+ VMSTATE_UINT32(vr, CPUOpenRISCState),
+ VMSTATE_UINT32(upr, CPUOpenRISCState),
+ VMSTATE_UINT32(cpucfgr, CPUOpenRISCState),
+ VMSTATE_UINT32(dmmucfgr, CPUOpenRISCState),
+ VMSTATE_UINT32(immucfgr, CPUOpenRISCState),
VMSTATE_UINT32(esr, CPUOpenRISCState),
VMSTATE_UINT32(fpcsr, CPUOpenRISCState),
- VMSTATE_UINT32(pc, CPUOpenRISCState),
- VMSTATE_UINT32(npc, CPUOpenRISCState),
- VMSTATE_UINT32(ppc, CPUOpenRISCState),
VMSTATE_END_OF_LIST()
}
};
diff --git a/target/openrisc/mmu.c b/target/openrisc/mmu.c
index 505dcdc..56b11d3 100644
--- a/target/openrisc/mmu.c
+++ b/target/openrisc/mmu.c
@@ -174,6 +174,7 @@ static void cpu_openrisc_raise_mmu_exception(OpenRISCCPU *cpu,
cs->exception_index = exception;
cpu->env.eear = address;
+ cpu->env.lock_addr = -1;
}
#ifndef CONFIG_USER_ONLY
diff --git a/target/openrisc/translate.c b/target/openrisc/translate.c
index 03fa7db..c207875 100644
--- a/target/openrisc/translate.c
+++ b/target/openrisc/translate.c
@@ -61,6 +61,8 @@ static TCGv jmp_pc; /* l.jr/l.jalr temp pc */
static TCGv cpu_npc;
static TCGv cpu_ppc;
static TCGv_i32 env_btaken; /* bf/bnf , F flag taken */
+static TCGv cpu_lock_addr;
+static TCGv cpu_lock_value;
static TCGv_i32 fpcsr;
static TCGv machi, maclo;
static TCGv fpmaddhi, fpmaddlo;
@@ -95,6 +97,12 @@ void openrisc_translate_init(void)
env_btaken = tcg_global_mem_new_i32(cpu_env,
offsetof(CPUOpenRISCState, btaken),
"btaken");
+ cpu_lock_addr = tcg_global_mem_new(cpu_env,
+ offsetof(CPUOpenRISCState, lock_addr),
+ "lock_addr");
+ cpu_lock_value = tcg_global_mem_new(cpu_env,
+ offsetof(CPUOpenRISCState, lock_value),
+ "lock_value");
fpcsr = tcg_global_mem_new_i32(cpu_env,
offsetof(CPUOpenRISCState, fpcsr),
"fpcsr");
@@ -265,6 +273,46 @@ static void gen_jump(DisasContext *dc, uint32_t imm, uint32_t reg, uint32_t op0)
}
+static void gen_lwa(DisasContext *dc, TCGv rd, TCGv ra, int32_t ofs)
+{
+ TCGv ea = tcg_temp_new();
+
+ tcg_gen_addi_tl(ea, ra, ofs);
+ tcg_gen_qemu_ld_tl(rd, ea, dc->mem_idx, MO_TEUL);
+ tcg_gen_mov_tl(cpu_lock_addr, ea);
+ tcg_gen_mov_tl(cpu_lock_value, rd);
+ tcg_temp_free(ea);
+}
+
+static void gen_swa(DisasContext *dc, TCGv rb, TCGv ra, int32_t ofs)
+{
+ TCGv ea, val;
+ TCGLabel *lab_fail, *lab_done;
+
+ ea = tcg_temp_new();
+ tcg_gen_addi_tl(ea, ra, ofs);
+
+ lab_fail = gen_new_label();
+ lab_done = gen_new_label();
+ tcg_gen_brcond_tl(TCG_COND_NE, ea, cpu_lock_addr, lab_fail);
+ tcg_temp_free(ea);
+
+ val = tcg_temp_new();
+ tcg_gen_atomic_cmpxchg_tl(val, cpu_lock_addr, cpu_lock_value,
+ rb, dc->mem_idx, MO_TEUL);
+ tcg_gen_setcond_tl(TCG_COND_EQ, env_btaken, val, cpu_lock_value);
+ tcg_temp_free(val);
+
+ tcg_gen_br(lab_done);
+
+ gen_set_label(lab_fail);
+ tcg_gen_movi_tl(env_btaken, 0);
+
+ gen_set_label(lab_done);
+ tcg_gen_movi_tl(cpu_lock_addr, -1);
+ wb_SR_F();
+}
+
static void dec_calc(DisasContext *dc, uint32_t insn)
{
uint32_t op0, op1, op2;
@@ -819,6 +867,11 @@ static void dec_misc(DisasContext *dc, uint32_t insn)
}
break;
+ case 0x1b: /* l.lwa */
+ LOG_DIS("l.lwa r%d, r%d, %d\n", rd, ra, I16);
+ gen_lwa(dc, cpu_R[rd], cpu_R[ra], I16);
+ break;
+
case 0x1c: /* l.cust1 */
LOG_DIS("l.cust1\n");
break;
@@ -1029,6 +1082,11 @@ static void dec_misc(DisasContext *dc, uint32_t insn)
}
break;
+ case 0x33: /* l.swa */
+ LOG_DIS("l.swa %d, r%d, r%d, %d\n", I5, ra, rb, I11);
+ gen_swa(dc, cpu_R[rb], cpu_R[ra], sign_extend(tmp, 16));
+ break;
+
/* not used yet, open it when we need or64. */
/*#ifdef TARGET_OPENRISC64
case 0x34: l.sd
--
2.9.3
next prev parent reply other threads:[~2017-02-09 4:52 UTC|newest]
Thread overview: 30+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-02-09 4:51 [Qemu-devel] [PATCH 00/22] target/openrisc updates Richard Henderson
2017-02-09 4:51 ` [Qemu-devel] [PATCH 01/22] target/openrisc: Rename the cpu from or32 to or1k Richard Henderson
2017-02-09 4:51 ` [Qemu-devel] [PATCH 03/22] linux-user: Fix openrisc cpu_loop Richard Henderson
2017-02-09 4:51 ` [Qemu-devel] [PATCH 04/22] target/openrisc: Fix exception handling status registers Richard Henderson
2017-02-09 4:51 ` [OpenRISC] " Richard Henderson
2017-02-09 4:51 ` Richard Henderson [this message]
2017-02-09 4:51 ` [Qemu-devel] [PATCH 06/22] target/openrisc: Tidy insn dumping Richard Henderson
2017-02-09 5:14 ` Philippe Mathieu-Daudé
2017-02-09 4:51 ` [Qemu-devel] [PATCH 07/22] target/openrisc: Rationalize immediate extraction Richard Henderson
2017-02-09 4:51 ` [Qemu-devel] [PATCH 08/22] target/openrisc: Streamline arithmetic and OVE Richard Henderson
2017-02-09 4:51 ` [Qemu-devel] [PATCH 09/22] target/openrisc: Put SR[OVE] in TB flags Richard Henderson
2017-02-09 4:51 ` [Qemu-devel] [PATCH 10/22] target/openrisc: Invert the decoding in dec_calc Richard Henderson
2017-02-09 4:51 ` [Qemu-devel] [PATCH 11/22] target/openrisc: Keep SR_F in a separate variable Richard Henderson
2017-02-09 4:51 ` [Qemu-devel] [PATCH 12/22] target/openrisc: Keep SR_CY and SR_OV in a separate variables Richard Henderson
2017-02-09 4:51 ` [Qemu-devel] [PATCH 13/22] target/openrisc: Use movcond where appropriate Richard Henderson
2017-02-09 4:51 ` [Qemu-devel] [PATCH 14/22] target/openrisc: Set flags on helpers Richard Henderson
2017-02-09 5:16 ` Philippe Mathieu-Daudé
2017-02-09 4:51 ` [Qemu-devel] [PATCH 15/22] target/openrisc: Enable trap, csync, msync, psync for user mode Richard Henderson
2017-02-09 5:24 ` Philippe Mathieu-Daudé
2017-02-09 4:51 ` [Qemu-devel] [PATCH 16/22] target/openrisc: Implement msync Richard Henderson
2017-02-09 4:51 ` [Qemu-devel] [PATCH 17/22] target/openrisc: Represent MACHI:MACLO as a single unit Richard Henderson
2017-02-09 4:51 ` [Qemu-devel] [PATCH 18/22] target/openrisc: Implement muld, muldu, macu, msbu Richard Henderson
2017-02-09 4:51 ` [Qemu-devel] [PATCH 19/22] target/openrisc: Fix madd Richard Henderson
2017-02-09 4:51 ` [Qemu-devel] [PATCH 20/22] target/openrisc: Optimize l.jal to next Richard Henderson
2017-02-09 5:20 ` Philippe Mathieu-Daudé
2017-02-09 4:51 ` [Qemu-devel] [PATCH 21/22] target/openrisc: Tidy ppc/npc implementation Richard Henderson
2017-02-09 4:51 ` [Qemu-devel] [PATCH 22/22] target/openrisc: Tidy handling of delayed branches Richard Henderson
2017-02-10 0:01 ` [Qemu-devel] [PATCH 23/22] linux-user: Honor CLONE_SETTLS for openrisc Richard Henderson
2017-02-10 0:44 ` Stafford Horne
2017-02-10 0:44 ` [OpenRISC] " Stafford Horne
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