From: Richard Henderson <rth@twiddle.net>
To: qemu-devel@nongnu.org
Cc: peter.maydell@linaro.org, David Hildenbrand <david@redhat.com>
Subject: [Qemu-devel] [PULL 02/15] target/s390x: change PSW_SHIFT_KEY
Date: Fri, 23 Jun 2017 09:22:28 -0700 [thread overview]
Message-ID: <20170623162241.8964-3-rth@twiddle.net> (raw)
In-Reply-To: <20170623162241.8964-1-rth@twiddle.net>
From: David Hildenbrand <david@redhat.com>
Such shifts are usually used to easily extract the PSW KEY from the PSW
mask, so let's avoid the confusing offset of 4.
Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Signed-off-by: David Hildenbrand <david@redhat.com>
Message-Id: <20170614133819.18480-2-david@redhat.com>
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
target/s390x/cpu.h | 2 +-
target/s390x/translate.c | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/target/s390x/cpu.h b/target/s390x/cpu.h
index a4028fb..532a4a0 100644
--- a/target/s390x/cpu.h
+++ b/target/s390x/cpu.h
@@ -315,7 +315,7 @@ void s390x_cpu_debug_excp_handler(CPUState *cs);
#define PSW_MASK_IO 0x0200000000000000ULL
#define PSW_MASK_EXT 0x0100000000000000ULL
#define PSW_MASK_KEY 0x00F0000000000000ULL
-#define PSW_SHIFT_KEY 56
+#define PSW_SHIFT_KEY 52
#define PSW_MASK_MCHECK 0x0004000000000000ULL
#define PSW_MASK_WAIT 0x0002000000000000ULL
#define PSW_MASK_PSTATE 0x0001000000000000ULL
diff --git a/target/s390x/translate.c b/target/s390x/translate.c
index 5a00279..6ebfb97 100644
--- a/target/s390x/translate.c
+++ b/target/s390x/translate.c
@@ -3753,7 +3753,7 @@ static ExitStatus op_spka(DisasContext *s, DisasOps *o)
{
check_privileged(s);
tcg_gen_shri_i64(o->in2, o->in2, 4);
- tcg_gen_deposit_i64(psw_mask, psw_mask, o->in2, PSW_SHIFT_KEY - 4, 4);
+ tcg_gen_deposit_i64(psw_mask, psw_mask, o->in2, PSW_SHIFT_KEY, 4);
return NO_EXIT;
}
--
2.9.4
next prev parent reply other threads:[~2017-06-23 16:22 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-06-23 16:22 [Qemu-devel] [PULL 00/15] Queued target/s390x patches Richard Henderson
2017-06-23 16:22 ` [Qemu-devel] [PULL 01/15] target/s390x: Map existing FAC_* names to S390_FEAT_* names Richard Henderson
2017-06-23 16:22 ` Richard Henderson [this message]
2017-06-23 16:22 ` [Qemu-devel] [PULL 03/15] target/s390x: implement mvcos instruction Richard Henderson
2017-06-23 16:22 ` [Qemu-devel] [PULL 04/15] target/s390x: Mark FPSEH facility as available Richard Henderson
2017-06-23 16:22 ` [Qemu-devel] [PULL 05/15] target/s390x: Implement load-on-condition-2 insns Richard Henderson
2017-06-23 16:22 ` [Qemu-devel] [PULL 07/15] target/s390x: Mark STFLE_53 facility as available Richard Henderson
2017-06-23 16:22 ` [Qemu-devel] [PULL 08/15] target/s390x: Implement execution-hint insns Richard Henderson
2017-06-23 16:22 ` [Qemu-devel] [PULL 09/15] target/s390x: Implement processor-assist insn Richard Henderson
2017-06-23 16:22 ` [Qemu-devel] [PULL 10/15] target/s390x: Mark STFLE_49 facility as available Richard Henderson
2017-06-23 16:22 ` [Qemu-devel] [PULL 11/15] target/s390x: Finish implementing ETF2-ENH Richard Henderson
2017-06-23 16:22 ` [Qemu-devel] [PULL 12/15] target/s390x: Clean up TB flag bits Richard Henderson
2017-06-23 16:22 ` [Qemu-devel] [PULL 13/15] target/s390x: Indicate and check for local tlb clearing Richard Henderson
2017-06-23 16:22 ` [Qemu-devel] [PULL 14/15] target/s390x: Improve heuristic for ipte Richard Henderson
2017-06-23 16:22 ` [Qemu-devel] [PULL 15/15] target/s390x: Implement idte instruction Richard Henderson
2017-06-26 9:17 ` [Qemu-devel] [PULL 00/15] Queued target/s390x patches Peter Maydell
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