Re: [PATCH v7 08/15] RISC-V: Atomic and Locking Code

From: Boqun Feng <boqun.feng@gmail.com>
To: Palmer Dabbelt <palmer@dabbelt.com>
Cc: peterz@infradead.org, tglx@linutronix.de, jason@lakedaemon.net,
	marc.zyngier@arm.com, Arnd Bergmann <arnd@arndb.de>,
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Subject: Re: [PATCH v7 08/15] RISC-V: Atomic and Locking Code
Date: Tue, 1 Aug 2017 13:31:59 +0800	[thread overview]
Message-ID: <20170801053159.h3ssqlznowicnsmg@tardis> (raw)
In-Reply-To: <20170801010009.3302-9-palmer@dabbelt.com>

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On Mon, Jul 31, 2017 at 06:00:02PM -0700, Palmer Dabbelt wrote:
> This contains all the code that directly interfaces with the RISC-V
> memory model.  While this code corforms to the current RISC-V ISA
> specifications (user 2.2 and priv 1.10), the memory model is somewhat
> underspecified in those documents.  There is a working group that hopes
> to produce a formal memory model by the end of the year, but my
> understanding is that the basic definitions we're relying on here won't
> change significantly.
> 
> Signed-off-by: Palmer Dabbelt <palmer@dabbelt.com>
> ---
>  arch/riscv/include/asm/atomic.h         | 328 ++++++++++++++++++++++++++++++++
>  arch/riscv/include/asm/barrier.h        |  68 +++++++
>  arch/riscv/include/asm/bitops.h         | 218 +++++++++++++++++++++
>  arch/riscv/include/asm/cacheflush.h     |  39 ++++
>  arch/riscv/include/asm/cmpxchg.h        | 134 +++++++++++++
>  arch/riscv/include/asm/io.h             | 303 +++++++++++++++++++++++++++++
>  arch/riscv/include/asm/spinlock.h       | 165 ++++++++++++++++
>  arch/riscv/include/asm/spinlock_types.h |  33 ++++
>  arch/riscv/include/asm/tlb.h            |  24 +++
>  arch/riscv/include/asm/tlbflush.h       |  64 +++++++
>  10 files changed, 1376 insertions(+)
>  create mode 100644 arch/riscv/include/asm/atomic.h
>  create mode 100644 arch/riscv/include/asm/barrier.h
>  create mode 100644 arch/riscv/include/asm/bitops.h
>  create mode 100644 arch/riscv/include/asm/cacheflush.h
>  create mode 100644 arch/riscv/include/asm/cmpxchg.h
>  create mode 100644 arch/riscv/include/asm/io.h
>  create mode 100644 arch/riscv/include/asm/spinlock.h
>  create mode 100644 arch/riscv/include/asm/spinlock_types.h
>  create mode 100644 arch/riscv/include/asm/tlb.h
>  create mode 100644 arch/riscv/include/asm/tlbflush.h
> 
> diff --git a/arch/riscv/include/asm/atomic.h b/arch/riscv/include/asm/atomic.h
> new file mode 100644
> index 000000000000..ee3ab06e492b
> --- /dev/null
> +++ b/arch/riscv/include/asm/atomic.h
> @@ -0,0 +1,328 @@
> +/*
> + * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
> + * Copyright (C) 2012 Regents of the University of California
> + * Copyright (C) 2017 SiFive
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public Licence
> + * as published by the Free Software Foundation; either version
> + * 2 of the Licence, or (at your option) any later version.
> + */
> +
> +#ifndef _ASM_RISCV_ATOMIC_H
> +#define _ASM_RISCV_ATOMIC_H
> +
> +#ifdef CONFIG_GENERIC_ATOMIC64
> +# include <asm-generic/atomic64.h>
> +#else
> +# if (__riscv_xlen < 64)
> +#  error "64-bit atomics require XLEN to be at least 64"
> +# endif
> +#endif
> +
> +#include <asm/cmpxchg.h>
> +#include <asm/barrier.h>
> +
> +#define ATOMIC_INIT(i)	{ (i) }
> +static __always_inline int atomic_read(const atomic_t *v)
> +{
> +	return READ_ONCE(v->counter);
> +}
> +static __always_inline void atomic_set(atomic_t *v, int i)
> +{
> +	WRITE_ONCE(v->counter, i);
> +}
> +
> +#ifndef CONFIG_GENERIC_ATOMIC64
> +#define ATOMIC64_INIT(i) { (i) }
> +static __always_inline int atomic64_read(const atomic64_t *v)
                         ^^^^^

should be "long long"?

> +{
> +	return READ_ONCE(v->counter);
> +}
> +static __always_inline void atomic64_set(atomic64_t *v, int i)
                                                          ^^^^^
Ditto.

Have you ever run the selftest with CONFIG_ATOMIC64_SELFTEST=y?

Regards,
Boqun

> +{
> +	WRITE_ONCE(v->counter, i);
> +}
> +#endif
> +
[...]

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