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From: "Subhransu S. Prusty" <subhransu.s.prusty@intel.com>
To: Stephen Boyd <sboyd@codeaurora.org>
Cc: Sriram Periyasamy <sriramx.periyasamy@intel.com>,
	ALSA ML <alsa-devel@alsa-project.org>,
	Mark Brown <broonie@kernel.org>, Takashi Iwai <tiwai@suse.de>,
	Liam Girdwood <liam.r.girdwood@linux.intel.com>,
	Vinod Koul <vinod.koul@intel.com>,
	Patches Audio <patches.audio@intel.com>,
	mturquette@baylibre.com, linux-clk@vger.kernel.org
Subject: Re: [alsa-devel] [PATCH v5 1/6] ASoC: Intel: Skylake: Add ssp clock driver
Date: Fri, 22 Dec 2017 10:22:30 +0530	[thread overview]
Message-ID: <20171222045229.GC21872@subhransu-desktop> (raw)
In-Reply-To: <20171222020436.GF7997@codeaurora.org>

On Thu, Dec 21, 2017 at 06:04:36PM -0800, Stephen Boyd wrote:
> On 12/20, Subhransu S. Prusty wrote:
> > On Tue, Dec 19, 2017 at 11:17:27AM -0800, Stephen Boyd wrote:
> > applicable here.
> 
> Yeah, let's ignore a changing parent frequency. recalc_rate() is
> also called when *this* clk rate is changed. The parent rate is
> passed in because that's usually helpful to calculate the rate
> that this op is supposed to return.
> 
> > 
> > For us, recalc_rate() doesn't mean much as we can only return current rate,
> > if it is same otherwise 0. Pls do advise in this case if the behaviour needs
> > to change, if so how?
> > 
> 
> Can the DSP tell us what the rate of the clk is? Or what the rate
> of the clk is configured for? What is that configuration out of
> boot when it's OFF? Typically, recalc_rate() can tell us what the

No, the DSP clock is programmed using configuration parameters which are
sent from driver. DSP doesn't have any mechanism to report the clock
configuration back to driver. So the rate is cached.

> rate of the clk is, even when its OFF, because we can read the
> hardware and calculate the rate of the clk given the parent
> frequency. We do have clk drivers out there that are like this
> DSP and don't tell anything about the rate and we can't even ask.
> In that case, we return 0 and cache the rate in the set_rate op.
> 
> Ideally, recalc_rate would always return the frequency of the clk
> that's been configured in the hardware on the DSP side. If that
> can't be done, I suppose faking it and caching the rate that the
> set_rate op figures out would work. Or if enabling the clk let's
> us know the rate we should cache it there too. But definitely

Yes, this behavior is applicable for this driver. I will remove the
recalculation part and resubmit the patch by returning the cached rate
already done in set_rate.

Regards,
Subhransu

> don't do any sort of rate caching in recalc_rate. It should just
> blindly return the cached value if it can't read hardware.
> 
> -- 
> Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
> a Linux Foundation Collaborative Project

-- 

  reply	other threads:[~2017-12-22  4:52 UTC|newest]

Thread overview: 24+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2017-12-11  7:46 [alsa-devel] [PATCH v5 0/6] ASoC: Intel: Skylake: Add a clk driver to enable ssp clks early Sriram Periyasamy
2017-12-11  7:46 ` [alsa-devel] [PATCH v5 1/6] ASoC: Intel: Skylake: Add ssp clock driver Sriram Periyasamy
2017-12-13 22:30   ` Stephen Boyd
2017-12-18  3:57     ` Subhransu S. Prusty
2017-12-18  5:01       ` Subhransu S. Prusty
2017-12-18 19:10         ` Stephen Boyd
2017-12-19  5:41           ` Subhransu S. Prusty
2017-12-19 19:17             ` Stephen Boyd
2017-12-20  3:33               ` Subhransu S. Prusty
2017-12-22  2:04                 ` Stephen Boyd
2017-12-22  4:52                   ` Subhransu S. Prusty [this message]
2017-12-11  7:46 ` [alsa-devel] [PATCH v5 2/6] ASoC: Intel: Skylake: Add extended I2S config blob support in Clock driver Sriram Periyasamy
2018-01-26 12:54   ` Applied "ASoC: Intel: Skylake: Add extended I2S config blob support in Clock driver" to the asoc tree Mark Brown
2018-01-26 12:54     ` Mark Brown
2017-12-11  7:46 ` [alsa-devel] [PATCH v5 3/6] ASoC: Intel: kbl: Enable mclk and ssp sclk early Sriram Periyasamy
2018-01-26 12:53   ` Applied "ASoC: Intel: kbl: Enable mclk and ssp sclk early" to the asoc tree Mark Brown
2018-01-26 12:53     ` Mark Brown
2017-12-11  7:46 ` [alsa-devel] [PATCH v5 4/6] ASoC: Intel: eve: Enable mclk and ssp sclk early Sriram Periyasamy
2017-12-11  7:46 ` [alsa-devel] [PATCH v5 5/6] ASoC: Intel: Skylake: Make DSP replies more human readable Sriram Periyasamy
2017-12-12 18:27   ` Patel, Chintan M
2017-12-12 18:27     ` Patel, Chintan M
2017-12-13  3:25     ` Vinod Koul
2017-12-13  3:25       ` Vinod Koul
2017-12-11  7:46 ` [alsa-devel] [PATCH v5 6/6] ASoC: Intel: Skylake: Add FW reply for MCLK/SCLK IPC Sriram Periyasamy

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