From: Patchwork <patchwork@emeril.freedesktop.org>
To: Paulo Zanoni <paulo.r.zanoni@intel.com>
Cc: intel-gfx@lists.freedesktop.org
Subject: ✗ Fi.CI.BAT: warning for ICL PLLs, DP/HDMI and misc display
Date: Thu, 22 Feb 2018 04:24:42 -0000 [thread overview]
Message-ID: <20180222042442.14813.66106@emeril.freedesktop.org> (raw)
In-Reply-To: <20180222035519.13486-1-paulo.r.zanoni@intel.com>
== Series Details ==
Series: ICL PLLs, DP/HDMI and misc display
URL : https://patchwork.freedesktop.org/series/38737/
State : warning
== Summary ==
Series 38737v1 ICL PLLs, DP/HDMI and misc display
https://patchwork.freedesktop.org/api/1.0/series/38737/revisions/1/mbox/
Test gem_exec_suspend:
Subgroup basic-s4-devices:
pass -> DMESG-WARN (fi-kbl-7500u)
Test gem_mmap_gtt:
Subgroup basic-small-bo-tiledx:
fail -> PASS (fi-gdg-551) fdo#102575
Test kms_chamelium:
Subgroup dp-edid-read:
pass -> FAIL (fi-kbl-7500u) fdo#102505
Test kms_pipe_crc_basic:
Subgroup suspend-read-crc-pipe-c:
incomplete -> PASS (fi-bxt-dsi) fdo#103927
fdo#102575
fdo#102505
fdo#103927
fi-bdw-5557u total:288 pass:267 dwarn:0 dfail:0 fail:0 skip:21 time:418s
fi-bdw-gvtdvm total:288 pass:264 dwarn:0 dfail:0 fail:0 skip:24 time:425s
fi-blb-e6850 total:288 pass:223 dwarn:1 dfail:0 fail:0 skip:64 time:375s
fi-bsw-n3050 total:288 pass:242 dwarn:0 dfail:0 fail:0 skip:46 time:490s
fi-bwr-2160 total:288 pass:183 dwarn:0 dfail:0 fail:0 skip:105 time:287s
fi-bxt-dsi total:288 pass:258 dwarn:0 dfail:0 fail:0 skip:30 time:480s
fi-bxt-j4205 total:288 pass:259 dwarn:0 dfail:0 fail:0 skip:29 time:479s
fi-byt-j1900 total:288 pass:253 dwarn:0 dfail:0 fail:0 skip:35 time:469s
fi-byt-n2820 total:288 pass:249 dwarn:0 dfail:0 fail:0 skip:39 time:459s
fi-cfl-s2 total:288 pass:262 dwarn:0 dfail:0 fail:0 skip:26 time:568s
fi-elk-e7500 total:288 pass:229 dwarn:0 dfail:0 fail:0 skip:59 time:414s
fi-gdg-551 total:288 pass:180 dwarn:0 dfail:0 fail:0 skip:108 time:284s
fi-glk-1 total:288 pass:260 dwarn:0 dfail:0 fail:0 skip:28 time:508s
fi-hsw-4770 total:288 pass:261 dwarn:0 dfail:0 fail:0 skip:27 time:385s
fi-ilk-650 total:288 pass:228 dwarn:0 dfail:0 fail:0 skip:60 time:411s
fi-ivb-3520m total:288 pass:259 dwarn:0 dfail:0 fail:0 skip:29 time:461s
fi-ivb-3770 total:288 pass:255 dwarn:0 dfail:0 fail:0 skip:33 time:408s
fi-kbl-7500u total:288 pass:261 dwarn:2 dfail:0 fail:1 skip:24 time:460s
fi-kbl-7560u total:288 pass:269 dwarn:0 dfail:0 fail:0 skip:19 time:489s
fi-kbl-7567u total:288 pass:268 dwarn:0 dfail:0 fail:0 skip:20 time:446s
fi-kbl-r total:288 pass:261 dwarn:0 dfail:0 fail:0 skip:27 time:492s
fi-pnv-d510 total:288 pass:222 dwarn:1 dfail:0 fail:0 skip:65 time:594s
fi-skl-6260u total:288 pass:268 dwarn:0 dfail:0 fail:0 skip:20 time:430s
fi-skl-6600u total:288 pass:261 dwarn:0 dfail:0 fail:0 skip:27 time:504s
fi-skl-6700hq total:288 pass:262 dwarn:0 dfail:0 fail:0 skip:26 time:523s
fi-skl-6700k2 total:288 pass:264 dwarn:0 dfail:0 fail:0 skip:24 time:491s
fi-skl-6770hq total:288 pass:268 dwarn:0 dfail:0 fail:0 skip:20 time:472s
fi-skl-guc total:288 pass:260 dwarn:0 dfail:0 fail:0 skip:28 time:406s
fi-skl-gvtdvm total:288 pass:265 dwarn:0 dfail:0 fail:0 skip:23 time:430s
fi-snb-2520m total:288 pass:248 dwarn:0 dfail:0 fail:0 skip:40 time:516s
fi-snb-2600 total:288 pass:248 dwarn:0 dfail:0 fail:0 skip:40 time:393s
42016703e66b7b572d4ab651946b715cdbff3050 drm-tip: 2018y-02m-21d-21h-26m-53s UTC integration manifest
b154a6a9c427 drm/i915/icl: Fix the DP Max Voltage for ICL
78a0633561af drm/i915/gen11: all the DDI ports on gen 11 support 4 lanes
f39480af7607 drm/i915/icl: Don't set pipe CSC/Gamma in PLANE_COLOR_CTL
137ca2ea6e11 drm/i915/icl: Calculate link clock using the new registers
390f90f94037 drm/i915/icl: Added 5k source scaling support for Gen11 platform
564b8c7a2810 drm/i915/icl: HPD pin for port F
a996d61691a8 drm/i915/icl: Implement voltage swing programming sequence for MG PHY DDI
87682ffe4e06 drm/i915/icl: Add Voltage swing table for MG PHY DDI Buffer
95188dc60dea drm/i915/icl: Add register defs for voltage swing sequences for MG PHY DDI
f68122f9a0b6 drm/i915/icl: Implement voltage swing programming sequence for Combo PHY DDI
7767df908beb drm/i915/icl: Add Combo PHY DDI Buffer translation tables for Icelake.
96d7a0b68153 drm/i915/icl: Add register definitions for Combo PHY vswing sequences.
756e2fb14b68 drm/i915/icl: compute the MG PLL registers
083e316a0ea3 drm/i915/icl: compute the combo PHY (DPLL) DP registers
394ce70a7d01 drm/i915/icl: compute the combo PHY (DPLL) HDMI registers
0212a3eaf876 drm/i915/icl: add basic support for the ICL clocks
176365bcdda2 drm/i915/icl: add definitions for the ICL PLL registers
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8116/issues.html
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next prev parent reply other threads:[~2018-02-22 4:24 UTC|newest]
Thread overview: 41+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-02-22 3:55 [PATCH 00/17] ICL PLLs, DP/HDMI and misc display Paulo Zanoni
2018-02-22 3:55 ` [PATCH 01/17] drm/i915/icl: add definitions for the ICL PLL registers Paulo Zanoni
2018-02-27 22:22 ` James Ausmus
2018-03-21 21:34 ` Paulo Zanoni
2018-03-23 0:07 ` Paulo Zanoni
2018-03-23 0:08 ` [PATCH 02/17] drm/i915/icl: add basic support for the ICL clocks Paulo Zanoni
2018-02-22 3:55 ` Paulo Zanoni
2018-02-28 0:40 ` James Ausmus
2018-02-22 3:55 ` [PATCH 03/17] drm/i915/icl: compute the combo PHY (DPLL) HDMI registers Paulo Zanoni
2018-02-28 19:59 ` James Ausmus
2018-02-22 3:55 ` [PATCH 04/17] drm/i915/icl: compute the combo PHY (DPLL) DP registers Paulo Zanoni
2018-02-28 20:12 ` James Ausmus
2018-02-22 3:55 ` [PATCH 05/17] drm/i915/icl: compute the MG PLL registers Paulo Zanoni
2018-03-01 23:35 ` Manasi Navare
2018-02-22 3:55 ` [PATCH 06/17] drm/i915/icl: Add register definitions for Combo PHY vswing sequences Paulo Zanoni
2018-02-22 3:55 ` [PATCH 07/17] drm/i915/icl: Add Combo PHY DDI Buffer translation tables for Icelake Paulo Zanoni
2018-02-22 3:55 ` [PATCH 08/17] drm/i915/icl: Implement voltage swing programming sequence for Combo PHY DDI Paulo Zanoni
2018-03-22 22:23 ` Paulo Zanoni
2018-03-23 0:10 ` Paulo Zanoni
2018-04-28 0:28 ` Rodrigo Vivi
2018-04-06 0:20 ` Rodrigo Vivi
2018-04-25 0:34 ` Paulo Zanoni
2018-04-25 18:01 ` Rodrigo Vivi
2018-04-25 23:33 ` Paulo Zanoni
2018-02-22 3:55 ` [PATCH 09/17] drm/i915/icl: Add register defs for voltage swing sequences for MG " Paulo Zanoni
2018-02-22 3:55 ` [PATCH 10/17] drm/i915/icl: Add Voltage swing table for MG PHY DDI Buffer Paulo Zanoni
2018-02-22 3:55 ` [PATCH 11/17] drm/i915/icl: Implement voltage swing programming sequence for MG PHY DDI Paulo Zanoni
2018-03-22 22:58 ` Paulo Zanoni
2018-02-22 3:55 ` [PATCH 12/17] drm/i915/icl: HPD pin for port F Paulo Zanoni
2018-02-22 20:16 ` Rodrigo Vivi
2018-02-22 3:55 ` [PATCH 13/17] drm/i915/icl: Added 5k source scaling support for Gen11 platform Paulo Zanoni
2018-02-22 3:55 ` [PATCH 14/17] drm/i915/icl: Calculate link clock using the new registers Paulo Zanoni
2018-03-22 23:20 ` Paulo Zanoni
2018-02-22 3:55 ` [PATCH 15/17] drm/i915/icl: Don't set pipe CSC/Gamma in PLANE_COLOR_CTL Paulo Zanoni
2018-02-22 3:55 ` [PATCH 16/17] drm/i915/gen11: all the DDI ports on gen 11 support 4 lanes Paulo Zanoni
2018-02-22 3:55 ` [PATCH 17/17] drm/i915/icl: Fix the DP Max Voltage for ICL Paulo Zanoni
2018-03-23 0:03 ` Rodrigo Vivi
2018-02-22 4:09 ` ✗ Fi.CI.CHECKPATCH: warning for ICL PLLs, DP/HDMI and misc display Patchwork
2018-02-22 4:24 ` Patchwork [this message]
2018-03-23 0:05 ` [PATCH 00/17] " Paulo Zanoni
2018-03-23 1:00 ` ✗ Fi.CI.BAT: failure for ICL PLLs, DP/HDMI and misc display (rev4) Patchwork
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