Re: [PATCH v6 09/14] drm/i915/gvt: Add 64K huge gtt support

From: "Du, Changbin" <changbin.du@intel.com>
To: Matthew Auld <matthew.william.auld@gmail.com>
Cc: Intel Graphics Development <intel-gfx@lists.freedesktop.org>,
	intel-gvt-dev@lists.freedesktop.org
Subject: Re: [PATCH v6 09/14] drm/i915/gvt: Add 64K huge gtt support
Date: Tue, 15 May 2018 08:01:55 +0800	[thread overview]
Message-ID: <20180515000155.bg7fm3ac522ywtsr@intel.com> (raw)
In-Reply-To: <CAM0jSHNoSJC1=GG_x+4ejddFEzGfcf9hxA3Z4mdYMcH9dqxGOQ@mail.gmail.com>

Hi Auld,
On Mon, May 14, 2018 at 09:31:54PM +0100, Matthew Auld wrote:
> On 8 May 2018 at 10:05,  <changbin.du@intel.com> wrote:
> > From: Changbin Du <changbin.du@intel.com>
> >
> > Finally, this add the first huge gtt support for GVTg - 64K pages. Since
> > 64K page and 4K page cannot be mixed on the same page table, so we always
> > split a 64K entry into small 4K page. And when unshadow guest 64K entry,
> > we need ensure all the shadowed entries in shadow page table also get
> > cleared.
> >
> > For page table which has 64K gtt entry, only PTE#0, PTE#16, PTE#32, ...
> > PTE#496 are used. Unused PTEs update should be ignored.
> >
> > Signed-off-by: Changbin Du <changbin.du@intel.com>
> > ---
> >  drivers/gpu/drm/i915/gvt/gtt.c | 86 +++++++++++++++++++++++++++++++++++++++---
> >  1 file changed, 80 insertions(+), 6 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/gvt/gtt.c b/drivers/gpu/drm/i915/gvt/gtt.c
> > index 30b15e4..2f13464 100644
> > --- a/drivers/gpu/drm/i915/gvt/gtt.c
> > +++ b/drivers/gpu/drm/i915/gvt/gtt.c
> > @@ -978,9 +978,12 @@ static int ppgtt_invalidate_spt(struct intel_vgpu_ppgtt_spt *spt)
> >                         ppgtt_invalidate_pte(spt, &e);
> >                         break;
> >                 case GTT_TYPE_PPGTT_PTE_64K_ENTRY:
> > +                       /* We don't setup 64K shadow entry so far. */
> > +                       WARN(1, "suspicious 64K gtt entry\n");
> > +                       continue;
> >                 case GTT_TYPE_PPGTT_PTE_2M_ENTRY:
> >                 case GTT_TYPE_PPGTT_PTE_1G_ENTRY:
> > -                       WARN(1, "GVT doesn't support 64K/2M/1GB page\n");
> > +                       WARN(1, "GVT doesn't support 2M/1GB page\n");
> >                         continue;
> >                 case GTT_TYPE_PPGTT_PML4_ENTRY:
> >                 case GTT_TYPE_PPGTT_PDP_ENTRY:
> > @@ -1073,9 +1076,44 @@ static inline void ppgtt_generate_shadow_entry(struct intel_gvt_gtt_entry *se,
> >         se->type = ge->type;
> >         se->val64 = ge->val64;
> >
> > +       /* Because we always split 64KB pages, so clear IPS in shadow PDE. */
> > +       if (se->type == GTT_TYPE_PPGTT_PDE_ENTRY)
> > +               ops->clear_ips(se);
> 
> IIUC we are disabling 64K entries for the spt(we clear the IPS bit),
> so what are we actually gaining by going through the trouble of
> supporting them in the guest, as opposed to just disabling them?
One of the goal to support huge gtt shadowing is to remove speical quirk for
vGPU in the guest gfx driver, though I finally found this is not a light change.
But we still can gain from this change, for example, fewer gtt update trap.

-- 
Thanks,
Changbin Du
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