All of lore.kernel.org
 help / color / mirror / Atom feed
From: Stafford Horne <shorne@gmail.com>
To: Peter Maydell <peter.maydell@linaro.org>
Cc: QEMU Development <qemu-devel@nongnu.org>,
	Richard Henderson <richard.henderson@linaro.org>,
	Stafford Horne <shorne@gmail.com>
Subject: [Qemu-devel] [PULL v2 08/25] target/openrisc: Split out is_user
Date: Tue,  3 Jul 2018 00:10:06 +0900	[thread overview]
Message-ID: <20180702151023.24532-9-shorne@gmail.com> (raw)
In-Reply-To: <20180702151023.24532-1-shorne@gmail.com>

From: Richard Henderson <richard.henderson@linaro.org>

This allows us to limit the amount of ifdefs and isolate
the test for usermode.

Reviewed-by: Stafford Horne <shorne@gmail.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Stafford Horne <shorne@gmail.com>
---
 target/openrisc/translate.c | 27 ++++++++++++---------------
 1 file changed, 12 insertions(+), 15 deletions(-)

diff --git a/target/openrisc/translate.c b/target/openrisc/translate.c
index a618d39242..db149986af 100644
--- a/target/openrisc/translate.c
+++ b/target/openrisc/translate.c
@@ -50,6 +50,15 @@ typedef struct DisasContext {
     target_ulong jmp_pc_imm;
 } DisasContext;
 
+static inline bool is_user(DisasContext *dc)
+{
+#ifdef CONFIG_USER_ONLY
+    return true;
+#else
+    return dc->mem_idx == MMU_USER_IDX;
+#endif
+}
+
 /* Include the auto-generated decoder.  */
 #include "decode.inc.c"
 
@@ -853,33 +862,25 @@ static bool trans_l_mfspr(DisasContext *dc, arg_l_mfspr *a, uint32_t insn)
 {
     check_r0_write(a->d);
 
-#ifdef CONFIG_USER_ONLY
-    gen_illegal_exception(dc);
-#else
-    if (dc->mem_idx == MMU_USER_IDX) {
+    if (is_user(dc)) {
         gen_illegal_exception(dc);
     } else {
         TCGv_i32 ti = tcg_const_i32(a->k);
         gen_helper_mfspr(cpu_R[a->d], cpu_env, cpu_R[a->d], cpu_R[a->a], ti);
         tcg_temp_free_i32(ti);
     }
-#endif
     return true;
 }
 
 static bool trans_l_mtspr(DisasContext *dc, arg_l_mtspr *a, uint32_t insn)
 {
-#ifdef CONFIG_USER_ONLY
-    gen_illegal_exception(dc);
-#else
-    if (dc->mem_idx == MMU_USER_IDX) {
+    if (is_user(dc)) {
         gen_illegal_exception(dc);
     } else {
         TCGv_i32 ti = tcg_const_i32(a->k);
         gen_helper_mtspr(cpu_env, cpu_R[a->a], cpu_R[a->b], ti);
         tcg_temp_free_i32(ti);
     }
-#endif
     return true;
 }
 
@@ -1104,16 +1105,12 @@ static bool trans_l_csync(DisasContext *dc, arg_l_csync *a, uint32_t insn)
 
 static bool trans_l_rfe(DisasContext *dc, arg_l_rfe *a, uint32_t insn)
 {
-#ifdef CONFIG_USER_ONLY
-    gen_illegal_exception(dc);
-#else
-    if (dc->mem_idx == MMU_USER_IDX) {
+    if (is_user(dc)) {
         gen_illegal_exception(dc);
     } else {
         gen_helper_rfe(cpu_env);
         dc->base.is_jmp = DISAS_EXIT;
     }
-#endif
     return true;
 }
 
-- 
2.17.0

  parent reply	other threads:[~2018-07-02 15:11 UTC|newest]

Thread overview: 35+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-07-02 15:09 [Qemu-devel] [PULL v2 00/25] OpenRISC updates for 3.0 Stafford Horne
2018-07-02 15:09 ` [Qemu-devel] [PULL v2 01/25] target/openrisc: Fix mtspr shadow gprs Stafford Horne
2018-07-02 15:10 ` [Qemu-devel] [PULL v2 02/25] target/openrisc: Add print_insn_or1k Stafford Horne
2018-07-02 15:10 ` [Qemu-devel] [PULL v2 03/25] target/openrisc: Log interrupts Stafford Horne
2018-07-02 15:10 ` [Qemu-devel] [PULL v2 04/25] target/openrisc: Remove DISAS_JUMP & DISAS_TB_JUMP Stafford Horne
2018-07-02 15:10 ` [Qemu-devel] [PULL v2 05/25] target/openrisc: Use exit_tb instead of CPU_INTERRUPT_EXITTB Stafford Horne
2018-07-02 15:10 ` [Qemu-devel] [PULL v2 06/25] target/openrisc: Fix singlestep_enabled Stafford Horne
2018-07-02 15:10 ` [Qemu-devel] [PULL v2 07/25] target/openrisc: Link more translation blocks Stafford Horne
2018-07-02 15:10 ` Stafford Horne [this message]
2018-07-02 15:10 ` [Qemu-devel] [PULL v2 09/25] target/openrisc: Exit the TB after l.mtspr Stafford Horne
2018-07-02 15:10 ` [Qemu-devel] [PULL v2 10/25] target/openrisc: Form the spr index from tcg Stafford Horne
2018-07-02 15:10 ` [Qemu-devel] [PULL v2 11/25] target/openrisc: Merge tlb allocation into CPUOpenRISCState Stafford Horne
2018-07-02 15:10 ` [Qemu-devel] [PULL v2 12/25] target/openrisc: Remove indirect function calls for mmu Stafford Horne
2018-07-02 15:10 ` [Qemu-devel] [PULL v2 13/25] target/openrisc: Merge mmu_helper.c into mmu.c Stafford Horne
2018-07-02 15:10 ` [Qemu-devel] [PULL v2 14/25] target/openrisc: Reduce tlb to a single dimension Stafford Horne
2018-07-02 15:10 ` [Qemu-devel] [PULL v2 15/25] target/openrisc: Fix tlb flushing in mtspr Stafford Horne
2018-07-02 15:10 ` [Qemu-devel] [PULL v2 16/25] target/openrisc: Fix cpu_mmu_index Stafford Horne
2018-07-02 15:10 ` [Qemu-devel] [PULL v2 17/25] target/openrisc: Use identical sizes for ITLB and DTLB Stafford Horne
2018-07-02 15:10 ` [Qemu-devel] [PULL v2 18/25] target/openrisc: Stub out handle_mmu_fault for softmmu Stafford Horne
2018-07-02 15:10 ` [Qemu-devel] [PULL v2 19/25] target/openrisc: Increase the TLB size Stafford Horne
2018-07-02 15:10 ` [Qemu-devel] [PULL v2 20/25] target/openrisc: Reorg tlb lookup Stafford Horne
2018-07-02 15:10 ` [Qemu-devel] [PULL v2 21/25] target/openrisc: Add support in scripts/qemu-binfmt-conf.sh Stafford Horne
2018-07-02 15:10 ` [Qemu-devel] [PULL v2 22/25] linux-user: Implement signals for openrisc Stafford Horne
2018-07-03 22:34   ` Philippe Mathieu-Daudé
2018-07-03 23:51     ` Stafford Horne
2018-07-04 20:54       ` Richard Henderson
2018-07-06 22:22         ` Eric Blake
2018-07-06 23:02           ` Stafford Horne
2018-07-07  8:10             ` Laurent Vivier
2018-07-07  7:04       ` Alex Bennée
2018-07-02 15:10 ` [Qemu-devel] [PULL v2 23/25] linux-user: Fix struct sigaltstack " Stafford Horne
2018-07-02 15:10 ` [Qemu-devel] [PULL v2 24/25] target/openrisc: Fix delay slot exception flag to match spec Stafford Horne
2018-07-02 15:10 ` [Qemu-devel] [PULL v2 25/25] target/openrisc: Fix writes to interrupt mask register Stafford Horne
2018-07-02 15:36 ` [Qemu-devel] [PULL v2 00/25] OpenRISC updates for 3.0 Peter Maydell
2018-07-03 13:53   ` Stafford Horne

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=20180702151023.24532-9-shorne@gmail.com \
    --to=shorne@gmail.com \
    --cc=peter.maydell@linaro.org \
    --cc=qemu-devel@nongnu.org \
    --cc=richard.henderson@linaro.org \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.