From: Simon Horman <horms@verge.net.au>
To: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Cc: linux-renesas-soc@vger.kernel.org,
Michael Turquette <mturquette@baylibre.com>,
Stephen Boyd <sboyd@codeaurora.org>,
Geert Uytterhoeven <geert+renesas@glider.be>,
linux-clk@vger.kernel.org
Subject: Re: [PATCH 1/4] clk: renesas: rcar-gen3-cpg: factor out cpg_reg_modify()
Date: Mon, 26 Nov 2018 09:22:06 +0100 [thread overview]
Message-ID: <20181126082206.tnbbvknhcc7n4kjg@verge.net.au> (raw)
In-Reply-To: <8cca22f7-dbd7-2da0-2f58-e490982d2f6c@cogentembedded.com>
On Thu, Nov 22, 2018 at 09:39:42PM +0300, Sergei Shtylyov wrote:
> There's quite often repeated sequence of a CPG register read-modify-write,
> so it seems worth factoring it out into a function -- this saves 68 bytes
> of the object code already (AArch64 gcc 4.8.5) and will save more with the
> next patches...
>
> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
next prev parent reply other threads:[~2018-11-26 19:15 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-11-22 18:37 [PATCH 0/4] Renesas R8A77980 CPG/MSSR RPC clock support Sergei Shtylyov
2018-11-22 18:39 ` [PATCH 1/4] clk: renesas: rcar-gen3-cpg: factor out cpg_reg_modify() Sergei Shtylyov
2018-11-23 9:44 ` Geert Uytterhoeven
2018-11-26 8:22 ` Simon Horman [this message]
2018-11-22 18:41 ` [PATCH 2/4] clk: renesas: rcar-gen3-cpg: add RPC clock Sergei Shtylyov
2018-11-23 12:55 ` Geert Uytterhoeven
2018-11-27 15:38 ` Sergei Shtylyov
2019-01-21 14:08 ` Geert Uytterhoeven
2018-11-22 18:43 ` [PATCH 3/4] clk: renesas: rcar-gen3-cpg: add RPCD2 clock Sergei Shtylyov
2018-11-23 12:58 ` Geert Uytterhoeven
2018-11-22 18:45 ` [PATCH 4/4] clk: renesas: r8a77980-cpg-mssr: add RPC clocks Sergei Shtylyov
2018-11-23 12:59 ` Geert Uytterhoeven
2018-11-27 17:45 ` Sergei Shtylyov
2018-11-27 17:51 ` Geert Uytterhoeven
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