From: "Cédric Le Goater" <clg@kaod.org>
To: David Gibson <david@gibson.dropbear.id.au>
Cc: "Suraj Jitindar Singh" <sjitindarsingh@gmail.com>,
qemu-ppc@nongnu.org, qemu-devel@nongnu.org,
"Benjamin Herrenschmidt" <benh@kernel.crashing.org>,
"Cédric Le Goater" <clg@kaod.org>
Subject: [Qemu-devel] [PATCH 10/12] target/ppc: Rename PATB/PATBE -> PATE
Date: Fri, 15 Feb 2019 18:00:27 +0100 [thread overview]
Message-ID: <20190215170029.15641-11-clg@kaod.org> (raw)
In-Reply-To: <20190215170029.15641-1-clg@kaod.org>
From: Benjamin Herrenschmidt <benh@kernel.crashing.org>
That "b" means "base address" and thus shouldn't be in the name
of actual entries and related constants.
This patch keeps the synthetic patb_entry field of the spapr
virtual hypervisor unchanged until I figure out if that has
an impact on the migration stream.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
target/ppc/cpu.h | 6 +++++-
target/ppc/mmu-book3s-v3.h | 11 ++++++++++-
target/ppc/mmu-radix64.h | 4 ++--
hw/ppc/spapr.c | 24 +++++++++++++++---------
hw/ppc/spapr_hcall.c | 22 ++++++++++++----------
target/ppc/mmu-radix64.c | 18 ++++++++++--------
6 files changed, 54 insertions(+), 31 deletions(-)
diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
index e7c9ca8f5f84..e1fee1a03496 100644
--- a/target/ppc/cpu.h
+++ b/target/ppc/cpu.h
@@ -317,6 +317,10 @@ struct ppc_slb_t {
#define SEGMENT_SHIFT_1T 40
#define SEGMENT_MASK_1T (~((1ULL << SEGMENT_SHIFT_1T) - 1))
+typedef struct ppc_v3_pate_t {
+ uint64_t dw0;
+ uint64_t dw1;
+} ppc_v3_pate_t;
/*****************************************************************************/
/* Machine state register bits definition */
@@ -1239,7 +1243,7 @@ struct PPCVirtualHypervisorClass {
hwaddr ptex, int n);
void (*store_hpte)(PPCVirtualHypervisor *vhyp, hwaddr ptex,
uint64_t pte0, uint64_t pte1);
- uint64_t (*get_patbe)(PPCVirtualHypervisor *vhyp);
+ void (*get_pate)(PPCVirtualHypervisor *vhyp, ppc_v3_pate_t *entry);
target_ulong (*encode_hpt_for_kvm_pr)(PPCVirtualHypervisor *vhyp);
};
diff --git a/target/ppc/mmu-book3s-v3.h b/target/ppc/mmu-book3s-v3.h
index 216ff296c088..8474dfec41d9 100644
--- a/target/ppc/mmu-book3s-v3.h
+++ b/target/ppc/mmu-book3s-v3.h
@@ -32,7 +32,16 @@
#define PTCR_PATS 0x000000000000001FULL /* Partition Table Size */
/* Partition Table Entry Fields */
-#define PATBE1_GR 0x8000000000000000
+#define PATE0_HR 0x8000000000000000
+
+/*
+ * WARNING: This field doesn't actually exist in the final version of
+ * the architecture and is unused by hardware. However, qemu uses it
+ * as an indication of a radix guest in the pseudo-PATB entry that it
+ * maintains for SPAPR guests and in the migration stream, so we need
+ * to keep it around
+ */
+#define PATE1_GR 0x8000000000000000
/* Process Table Entry */
struct prtb_entry {
diff --git a/target/ppc/mmu-radix64.h b/target/ppc/mmu-radix64.h
index 0ecf063a1751..96228546aa85 100644
--- a/target/ppc/mmu-radix64.h
+++ b/target/ppc/mmu-radix64.h
@@ -12,8 +12,8 @@
#define R_EADDR_QUADRANT3 0xC000000000000000
/* Radix Partition Table Entry Fields */
-#define PATBE1_R_PRTB 0x0FFFFFFFFFFFF000
-#define PATBE1_R_PRTS 0x000000000000001F
+#define PATE1_R_PRTB 0x0FFFFFFFFFFFF000
+#define PATE1_R_PRTS 0x000000000000001F
/* Radix Process Table Entry Fields */
#define PRTBE_R_GET_RTS(rts) \
diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c
index 1afe31ee6163..c77507b82473 100644
--- a/hw/ppc/spapr.c
+++ b/hw/ppc/spapr.c
@@ -1403,11 +1403,13 @@ void spapr_set_all_lpcrs(target_ulong value, target_ulong mask)
}
}
-static uint64_t spapr_get_patbe(PPCVirtualHypervisor *vhyp)
+static void spapr_get_pate(PPCVirtualHypervisor *vhyp, ppc_v3_pate_t *entry)
{
sPAPRMachineState *spapr = SPAPR_MACHINE(vhyp);
- return spapr->patb_entry;
+ /* Copy PATE1:GR into PATE0:HR */
+ entry->dw0 = spapr->patb_entry & PATE0_HR;
+ entry->dw1 = spapr->patb_entry;
}
#define HPTE(_table, _i) (void *)(((uint64_t *)(_table)) + ((_i) * 2))
@@ -1650,17 +1652,21 @@ static void spapr_machine_reset(void)
if (kvm_enabled() && kvmppc_has_cap_mmu_radix() &&
ppc_type_check_compat(machine->cpu_type, CPU_POWERPC_LOGICAL_3_00, 0,
spapr->max_compat_pvr)) {
- /* If using KVM with radix mode available, VCPUs can be started
+ /*
+ * If using KVM with radix mode available, VCPUs can be started
* without a HPT because KVM will start them in radix mode.
- * Set the GR bit in PATB so that we know there is no HPT. */
- spapr->patb_entry = PATBE1_GR;
+ * Set the GR bit in PATE so that we know there is no HPT.
+ */
+ spapr->patb_entry = PATE1_GR;
spapr_set_all_lpcrs(LPCR_HR | LPCR_UPRT, LPCR_HR | LPCR_UPRT);
} else {
spapr_setup_hpt_and_vrma(spapr);
}
- /* if this reset wasn't generated by CAS, we should reset our
- * negotiated options and start from scratch */
+ /*
+ * If this reset wasn't generated by CAS, we should reset our
+ * negotiated options and start from scratch
+ */
if (!spapr->cas_reboot) {
spapr_ovec_cleanup(spapr->ov5_cas);
spapr->ov5_cas = spapr_ovec_new();
@@ -1810,7 +1816,7 @@ static int spapr_post_load(void *opaque, int version_id)
if (kvm_enabled() && spapr->patb_entry) {
PowerPCCPU *cpu = POWERPC_CPU(first_cpu);
- bool radix = !!(spapr->patb_entry & PATBE1_GR);
+ bool radix = !!(spapr->patb_entry & PATE1_GR);
bool gtse = !!(cpu->env.spr[SPR_LPCR] & LPCR_GTSE);
/*
@@ -4060,7 +4066,7 @@ static void spapr_machine_class_init(ObjectClass *oc, void *data)
vhc->map_hptes = spapr_map_hptes;
vhc->unmap_hptes = spapr_unmap_hptes;
vhc->store_hpte = spapr_store_hpte;
- vhc->get_patbe = spapr_get_patbe;
+ vhc->get_pate = spapr_get_pate;
vhc->encode_hpt_for_kvm_pr = spapr_encode_hpt_for_kvm_pr;
xic->ics_get = spapr_ics_get;
xic->ics_resend = spapr_ics_resend;
diff --git a/hw/ppc/spapr_hcall.c b/hw/ppc/spapr_hcall.c
index 2f64c69a6abf..54922b50aadb 100644
--- a/hw/ppc/spapr_hcall.c
+++ b/hw/ppc/spapr_hcall.c
@@ -1310,12 +1310,12 @@ static void spapr_check_setup_free_hpt(sPAPRMachineState *spapr,
* later and so assumed radix and now it's called H_REG_PROC_TBL
*/
- if ((patbe_old & PATBE1_GR) == (patbe_new & PATBE1_GR)) {
+ if ((patbe_old & PATE1_GR) == (patbe_new & PATE1_GR)) {
/* We assume RADIX, so this catches all the "Do Nothing" cases */
- } else if (!(patbe_old & PATBE1_GR)) {
+ } else if (!(patbe_old & PATE1_GR)) {
/* HASH->RADIX : Free HPT */
spapr_free_hpt(spapr);
- } else if (!(patbe_new & PATBE1_GR)) {
+ } else if (!(patbe_new & PATE1_GR)) {
/* RADIX->HASH || NOTHING->HASH : Allocate HPT */
spapr_setup_hpt_and_vrma(spapr);
}
@@ -1353,7 +1353,7 @@ static target_ulong h_register_process_table(PowerPCCPU *cpu,
} else if (table_size > 24) {
return H_P4;
}
- cproc = PATBE1_GR | proc_tbl | table_size;
+ cproc = PATE1_GR | proc_tbl | table_size;
} else { /* Register new HPT process table */
if (flags & FLAG_HASH_PROC_TBL) { /* Hash with Segment Tables */
/* TODO - Not Supported */
@@ -1372,13 +1372,15 @@ static target_ulong h_register_process_table(PowerPCCPU *cpu,
}
} else { /* Deregister current process table */
- /* Set to benign value: (current GR) | 0. This allows
- * deregistration in KVM to succeed even if the radix bit in flags
- * doesn't match the radix bit in the old PATB. */
- cproc = spapr->patb_entry & PATBE1_GR;
+ /*
+ * Set to benign value: (current GR) | 0. This allows
+ * deregistration in KVM to succeed even if the radix bit
+ * in flags doesn't match the radix bit in the old PATE.
+ */
+ cproc = spapr->patb_entry & PATE1_GR;
}
} else { /* Maintain current registration */
- if (!(flags & FLAG_RADIX) != !(spapr->patb_entry & PATBE1_GR)) {
+ if (!(flags & FLAG_RADIX) != !(spapr->patb_entry & PATE1_GR)) {
/* Technically caused by flag bits => H_PARAMETER */
return H_PARAMETER; /* Existing Process Table Mismatch */
}
@@ -1615,7 +1617,7 @@ static target_ulong h_client_architecture_support(PowerPCCPU *cpu,
if (!spapr->cas_reboot) {
/* If spapr_machine_reset() did not set up a HPT but one is necessary
* (because the guest isn't going to use radix) then set it up here. */
- if ((spapr->patb_entry & PATBE1_GR) && !guest_radix) {
+ if ((spapr->patb_entry & PATE1_GR) && !guest_radix) {
/* legacy hash or new hash: */
spapr_setup_hpt_and_vrma(spapr);
}
diff --git a/target/ppc/mmu-radix64.c b/target/ppc/mmu-radix64.c
index 5881efeb8598..f596f3c7774e 100644
--- a/target/ppc/mmu-radix64.c
+++ b/target/ppc/mmu-radix64.c
@@ -193,8 +193,9 @@ int ppc_radix64_handle_mmu_fault(PowerPCCPU *cpu, vaddr eaddr, int rwx,
PPCVirtualHypervisorClass *vhc =
PPC_VIRTUAL_HYPERVISOR_GET_CLASS(cpu->vhyp);
hwaddr raddr, pte_addr;
- uint64_t lpid = 0, pid = 0, offset, size, patbe, prtbe0, pte;
+ uint64_t lpid = 0, pid = 0, offset, size, prtbe0, pte;
int page_size, prot, fault_cause = 0;
+ ppc_v3_pate_t pate;
assert((rwx == 0) || (rwx == 1) || (rwx == 2));
assert(!msr_hv); /* For now there is no Radix PowerNV Support */
@@ -219,17 +220,17 @@ int ppc_radix64_handle_mmu_fault(PowerPCCPU *cpu, vaddr eaddr, int rwx,
}
/* Get Process Table */
- patbe = vhc->get_patbe(cpu->vhyp);
+ vhc->get_pate(cpu->vhyp, &pate);
/* Index Process Table by PID to Find Corresponding Process Table Entry */
offset = pid * sizeof(struct prtb_entry);
- size = 1ULL << ((patbe & PATBE1_R_PRTS) + 12);
+ size = 1ULL << ((pate.dw1 & PATE1_R_PRTS) + 12);
if (offset >= size) {
/* offset exceeds size of the process table */
ppc_radix64_raise_si(cpu, rwx, eaddr, DSISR_NOPTE);
return 1;
}
- prtbe0 = ldq_phys(cs->as, (patbe & PATBE1_R_PRTB) + offset);
+ prtbe0 = ldq_phys(cs->as, (pate.dw1 & PATE1_R_PRTB) + offset);
/* Walk Radix Tree from Process Table Entry to Convert EA to RA */
page_size = PRTBE_R_GET_RTS(prtbe0);
@@ -257,8 +258,9 @@ hwaddr ppc_radix64_get_phys_page_debug(PowerPCCPU *cpu, target_ulong eaddr)
PPCVirtualHypervisorClass *vhc =
PPC_VIRTUAL_HYPERVISOR_GET_CLASS(cpu->vhyp);
hwaddr raddr, pte_addr;
- uint64_t lpid = 0, pid = 0, offset, size, patbe, prtbe0, pte;
+ uint64_t lpid = 0, pid = 0, offset, size, prtbe0, pte;
int page_size, fault_cause = 0;
+ ppc_v3_pate_t pate;
/* Handle Real Mode */
if (msr_dr == 0) {
@@ -272,16 +274,16 @@ hwaddr ppc_radix64_get_phys_page_debug(PowerPCCPU *cpu, target_ulong eaddr)
}
/* Get Process Table */
- patbe = vhc->get_patbe(cpu->vhyp);
+ vhc->get_pate(cpu->vhyp, &pate);
/* Index Process Table by PID to Find Corresponding Process Table Entry */
offset = pid * sizeof(struct prtb_entry);
- size = 1ULL << ((patbe & PATBE1_R_PRTS) + 12);
+ size = 1ULL << ((pate.dw1 & PATE1_R_PRTS) + 12);
if (offset >= size) {
/* offset exceeds size of the process table */
return -1;
}
- prtbe0 = ldq_phys(cs->as, (patbe & PATBE1_R_PRTB) + offset);
+ prtbe0 = ldq_phys(cs->as, (pate.dw1 & PATE1_R_PRTB) + offset);
/* Walk Radix Tree from Process Table Entry to Convert EA to RA */
page_size = PRTBE_R_GET_RTS(prtbe0);
--
2.20.1
next prev parent reply other threads:[~2019-02-15 17:01 UTC|newest]
Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-02-15 17:00 [Qemu-devel] [PATCH 00/12] ppc: add native hash and radix support for POWER9 Cédric Le Goater
2019-02-15 17:00 ` [Qemu-devel] [PATCH 01/12] target/ppc/spapr: Set LPCR:HR when using Radix mode Cédric Le Goater
2019-02-18 6:12 ` David Gibson
2019-02-15 17:00 ` [Qemu-devel] [PATCH 02/12] target/ppci/mmu: Use LPCR:HR to chose radix vs. hash translation Cédric Le Goater
2019-02-18 6:47 ` David Gibson
2019-02-18 21:20 ` Philippe Mathieu-Daudé
2019-02-19 3:09 ` David Gibson
2019-02-15 17:00 ` [Qemu-devel] [PATCH 03/12] target/ppc: Re-enable RMLS on POWER9 for virtual hypervisors Cédric Le Goater
2019-02-19 3:46 ` David Gibson
2019-02-15 17:00 ` [Qemu-devel] [PATCH 04/12] target/ppc: Fix #include guard in mmu-book3s-v3.h Cédric Le Goater
2019-02-19 3:47 ` David Gibson
2019-02-15 17:00 ` [Qemu-devel] [PATCH 05/12] target/ppc: Cleanup 64-bit MMU includes Cédric Le Goater
2019-02-19 3:49 ` David Gibson
2019-02-15 17:00 ` [Qemu-devel] [PATCH 06/12] target/ppc: Fix ordering of hash MMU accesses Cédric Le Goater
2019-02-19 3:52 ` David Gibson
2019-02-15 17:00 ` [Qemu-devel] [PATCH 07/12] target/ppc: Add basic support for "new format" HPTE as found on POWER9 Cédric Le Goater
2019-02-19 4:05 ` David Gibson
2019-02-19 4:39 ` David Gibson
2019-02-15 17:00 ` [Qemu-devel] [PATCH 08/12] target/ppc: Fix synchronization of mttcg with broadcast TLB flushes Cédric Le Goater
2019-02-15 17:00 ` [Qemu-devel] [PATCH 09/12] target/ppc: Flush the TLB locally when the LPIDR is written Cédric Le Goater
2019-02-15 17:00 ` Cédric Le Goater [this message]
2019-02-15 17:00 ` [Qemu-devel] [PATCH 11/12] target/ppc: Support for POWER9 native hash Cédric Le Goater
2019-02-15 17:00 ` [Qemu-devel] [PATCH 12/12] target/ppc: Basic POWER9 bare-metal radix MMU support Cédric Le Goater
2019-02-19 5:19 ` [Qemu-devel] [PATCH 00/12] ppc: add native hash and radix support for POWER9 David Gibson
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