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From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Subject: [Qemu-devel] [PATCH 03/26] target/alpha: Convert to CPUClass::tlb_fill
Date: Wed,  3 Apr 2019 10:43:35 +0700	[thread overview]
Message-ID: <20190403034358.21999-4-richard.henderson@linaro.org> (raw)
In-Reply-To: <20190403034358.21999-1-richard.henderson@linaro.org>

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 target/alpha/cpu.h        |  5 ++--
 target/alpha/cpu.c        |  5 ++--
 target/alpha/helper.c     | 50 +++++++++++++++++++++++----------------
 target/alpha/mem_helper.c | 16 -------------
 4 files changed, 35 insertions(+), 41 deletions(-)

diff --git a/target/alpha/cpu.h b/target/alpha/cpu.h
index 7b50be785d..aecf8d75c1 100644
--- a/target/alpha/cpu.h
+++ b/target/alpha/cpu.h
@@ -476,8 +476,9 @@ void alpha_cpu_list(FILE *f, fprintf_function cpu_fprintf);
    is returned if the signal was handled by the virtual CPU.  */
 int cpu_alpha_signal_handler(int host_signum, void *pinfo,
                              void *puc);
-int alpha_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int size, int rw,
-                               int mmu_idx);
+bool alpha_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
+                        MMUAccessType access_type, int mmu_idx,
+                        bool probe, uintptr_t retaddr);
 void QEMU_NORETURN dynamic_excp(CPUAlphaState *, uintptr_t, int, int);
 void QEMU_NORETURN arith_excp(CPUAlphaState *, uintptr_t, int, uint64_t);
 
diff --git a/target/alpha/cpu.c b/target/alpha/cpu.c
index 1fd95d6c0f..5aa4581b9f 100644
--- a/target/alpha/cpu.c
+++ b/target/alpha/cpu.c
@@ -230,9 +230,8 @@ static void alpha_cpu_class_init(ObjectClass *oc, void *data)
     cc->set_pc = alpha_cpu_set_pc;
     cc->gdb_read_register = alpha_cpu_gdb_read_register;
     cc->gdb_write_register = alpha_cpu_gdb_write_register;
-#ifdef CONFIG_USER_ONLY
-    cc->handle_mmu_fault = alpha_cpu_handle_mmu_fault;
-#else
+    cc->tlb_fill = alpha_cpu_tlb_fill;
+#ifndef CONFIG_USER_ONLY
     cc->do_transaction_failed = alpha_cpu_do_transaction_failed;
     cc->do_unaligned_access = alpha_cpu_do_unaligned_access;
     cc->get_phys_page_debug = alpha_cpu_get_phys_page_debug;
diff --git a/target/alpha/helper.c b/target/alpha/helper.c
index 57e2c212b3..e54197d5fb 100644
--- a/target/alpha/helper.c
+++ b/target/alpha/helper.c
@@ -102,17 +102,7 @@ void cpu_alpha_store_gr(CPUAlphaState *env, unsigned reg, uint64_t val)
     *cpu_alpha_addr_gr(env, reg) = val;
 }
 
-#if defined(CONFIG_USER_ONLY)
-int alpha_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int size,
-                               int rw, int mmu_idx)
-{
-    AlphaCPU *cpu = ALPHA_CPU(cs);
-
-    cs->exception_index = EXCP_MMFAULT;
-    cpu->env.trap_arg0 = address;
-    return 1;
-}
-#else
+#ifndef CONFIG_USER_ONLY
 /* Returns the OSF/1 entMM failure indication, or -1 on success.  */
 static int get_physical_address(CPUAlphaState *env, target_ulong addr,
                                 int prot_need, int mmu_idx,
@@ -246,29 +236,49 @@ hwaddr alpha_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
     fail = get_physical_address(&cpu->env, addr, 0, 0, &phys, &prot);
     return (fail >= 0 ? -1 : phys);
 }
+#endif /* !USER_ONLY */
 
-int alpha_cpu_handle_mmu_fault(CPUState *cs, vaddr addr, int size, int rw,
-                               int mmu_idx)
+bool alpha_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
+                        MMUAccessType access_type, int mmu_idx,
+                        bool probe, uintptr_t retaddr)
 {
     AlphaCPU *cpu = ALPHA_CPU(cs);
+
+#ifdef CONFIG_USER_ONLY
+    cs->exception_index = EXCP_MMFAULT;
+    cpu->env.trap_arg0 = address;
+    cpu_loop_exit_restore(cs, retaddr);
+#else
     CPUAlphaState *env = &cpu->env;
     target_ulong phys;
     int prot, fail;
 
-    fail = get_physical_address(env, addr, 1 << rw, mmu_idx, &phys, &prot);
+    fail = get_physical_address(env, address, 1 << access_type,
+                                mmu_idx, &phys, &prot);
     if (unlikely(fail >= 0)) {
+        if (probe) {
+            return false;
+        }
         cs->exception_index = EXCP_MMFAULT;
-        env->trap_arg0 = addr;
+        env->trap_arg0 = address;
         env->trap_arg1 = fail;
-        env->trap_arg2 = (rw == 2 ? -1 : rw);
-        return 1;
+        env->trap_arg2 = (access_type == MMU_INST_FETCH ? -1 : access_type);
+        cpu_loop_exit_restore(cs, retaddr);
     }
 
-    tlb_set_page(cs, addr & TARGET_PAGE_MASK, phys & TARGET_PAGE_MASK,
+    tlb_set_page(cs, address & TARGET_PAGE_MASK, phys & TARGET_PAGE_MASK,
                  prot, mmu_idx, TARGET_PAGE_SIZE);
-    return 0;
+    return true;
+#endif
 }
-#endif /* USER_ONLY */
+
+#ifndef CONFIG_USER_ONLY
+void tlb_fill(CPUState *cs, target_ulong addr, int size,
+              MMUAccessType access_type, int mmu_idx, uintptr_t retaddr)
+{
+    alpha_cpu_tlb_fill(cs, addr, size, access_type, mmu_idx, false, retaddr);
+}
+#endif
 
 void alpha_cpu_do_interrupt(CPUState *cs)
 {
diff --git a/target/alpha/mem_helper.c b/target/alpha/mem_helper.c
index 011bc73dca..934faa1d6f 100644
--- a/target/alpha/mem_helper.c
+++ b/target/alpha/mem_helper.c
@@ -62,20 +62,4 @@ void alpha_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr,
     env->error_code = 0;
     cpu_loop_exit_restore(cs, retaddr);
 }
-
-/* try to fill the TLB and return an exception if error. If retaddr is
-   NULL, it means that the function was called in C code (i.e. not
-   from generated code or from helper.c) */
-/* XXX: fix it to restore all registers */
-void tlb_fill(CPUState *cs, target_ulong addr, int size,
-              MMUAccessType access_type, int mmu_idx, uintptr_t retaddr)
-{
-    int ret;
-
-    ret = alpha_cpu_handle_mmu_fault(cs, addr, size, access_type, mmu_idx);
-    if (unlikely(ret != 0)) {
-        /* Exception index and error code are already set */
-        cpu_loop_exit_restore(cs, retaddr);
-    }
-}
 #endif /* CONFIG_USER_ONLY */
-- 
2.17.1

  parent reply	other threads:[~2019-04-03  3:44 UTC|newest]

Thread overview: 89+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-04-03  3:43 [Qemu-devel] [PATCH 00/26] tcg: Add CPUClass::tlb_fill Richard Henderson
2019-04-03  3:43 ` [Qemu-devel] [PATCH 01/26] tcg: Assert h2g_valid for 32-bit guest on 64-bit host Richard Henderson
2019-04-03  4:59   ` Peter Maydell
2019-04-03  7:30     ` Richard Henderson
2019-04-03  3:43 ` [Qemu-devel] [PATCH 02/26] tcg: Add CPUClass::tlb_fill Richard Henderson
2019-04-29 17:25   ` Peter Maydell
2019-05-08  5:58     ` Philippe Mathieu-Daudé
2019-04-03  3:43 ` Richard Henderson [this message]
2019-04-29 17:47   ` [Qemu-devel] [PATCH 03/26] target/alpha: Convert to CPUClass::tlb_fill Peter Maydell
2019-05-08  6:09   ` Philippe Mathieu-Daudé
2019-04-03  3:43 ` [Qemu-devel] [PATCH 04/26] target/arm: " Richard Henderson
2019-04-03  5:14   ` [Qemu-devel] [Qemu-arm] " Peter Maydell
2019-04-03  7:30     ` Richard Henderson
2019-04-30 12:02     ` Peter Maydell
2019-04-30 12:02       ` Peter Maydell
2019-04-03  3:43 ` [Qemu-devel] [PATCH 05/26] target/cris: " Richard Henderson
2019-04-30 11:57   ` Peter Maydell
2019-04-30 11:57     ` Peter Maydell
2019-04-03  3:43 ` [Qemu-devel] [PATCH 06/26] target/hppa: " Richard Henderson
2019-04-30 11:51   ` Peter Maydell
2019-05-08  6:07   ` Philippe Mathieu-Daudé
2019-04-03  3:43 ` [Qemu-devel] [PATCH 07/26] target/i386: " Richard Henderson
2019-04-30 11:49   ` Peter Maydell
2019-04-30 11:49     ` Peter Maydell
2019-04-30 14:52     ` Richard Henderson
2019-04-30 14:52       ` Richard Henderson
2019-04-03  3:43 ` [Qemu-devel] [PATCH 08/26] target/lm32: " Richard Henderson
2019-04-30 11:45   ` Peter Maydell
2019-04-30 11:45     ` Peter Maydell
2019-04-03  3:43 ` [Qemu-devel] [PATCH 09/26] target/m68k: " Richard Henderson
2019-04-30 11:43   ` Peter Maydell
2019-04-03  3:43 ` [Qemu-devel] [PATCH 10/26] target/microblaze: " Richard Henderson
2019-04-30 11:04   ` Peter Maydell
2019-04-30 11:04     ` Peter Maydell
2019-04-03  3:43 ` [Qemu-devel] [PATCH 11/26] target/mips: " Richard Henderson
2019-04-30 10:57   ` Peter Maydell
2019-04-30 10:57     ` Peter Maydell
2019-05-08  5:55   ` Philippe Mathieu-Daudé
2019-04-03  3:43 ` [Qemu-devel] [PATCH 12/26] target/moxie: " Richard Henderson
2019-04-30 10:47   ` Peter Maydell
2019-04-30 10:47     ` Peter Maydell
2019-04-03  3:43 ` [Qemu-devel] [PATCH 13/26] target/nios2: " Richard Henderson
2019-04-30  9:44   ` Peter Maydell
2019-04-30  9:44     ` Peter Maydell
2019-04-03  3:43 ` [Qemu-devel] [PATCH 14/26] target/openrisc: " Richard Henderson
2019-04-30  9:31   ` Peter Maydell
2019-04-30  9:31     ` Peter Maydell
2019-04-03  3:43 ` [Qemu-devel] [PATCH 15/26] target/ppc: " Richard Henderson
2019-04-30  9:35   ` Peter Maydell
2019-04-30  9:35     ` Peter Maydell
2019-04-03  3:43 ` [Qemu-devel] [PATCH 16/26] target/riscv: " Richard Henderson
2019-04-03  3:43   ` [Qemu-riscv] " Richard Henderson
2019-04-03 23:02   ` [Qemu-devel] " Alistair Francis
2019-04-03 23:02     ` [Qemu-riscv] " Alistair Francis
2019-04-03  3:43 ` [Qemu-devel] [PATCH 17/26] target/s390x: " Richard Henderson
2019-04-03 11:17   ` David Hildenbrand
2019-05-09  1:53     ` Richard Henderson
2019-04-03  3:43 ` [Qemu-devel] [PATCH 18/26] target/sh4: " Richard Henderson
2019-04-29 17:59   ` Peter Maydell
2019-04-03  3:43 ` [Qemu-devel] [PATCH 19/26] target/sparc: " Richard Henderson
2019-04-03  4:36   ` Richard Henderson
2019-04-03  3:43 ` [Qemu-devel] [PATCH 20/26] target/tilegx: " Richard Henderson
2019-04-30 10:01   ` Peter Maydell
2019-04-03  3:43 ` [Qemu-devel] [PATCH 21/26] target/tricore: " Richard Henderson
2019-04-30 10:03   ` Peter Maydell
2019-04-30 10:03     ` Peter Maydell
2019-04-03  3:43 ` [Qemu-devel] [PATCH 22/26] target/unicore32: " Richard Henderson
2019-04-30 10:06   ` Peter Maydell
2019-04-30 10:06     ` Peter Maydell
2019-05-08  4:27     ` Guan Xuetao
2019-04-03  3:43 ` [Qemu-devel] [PATCH 23/26] target/xtensa: " Richard Henderson
2019-04-30 10:11   ` Peter Maydell
2019-04-30 10:11     ` Peter Maydell
2019-04-30 17:32     ` Max Filippov
2019-04-30 17:44       ` Richard Henderson
2019-04-30 18:14         ` Max Filippov
2019-04-30 21:07           ` Max Filippov
2019-05-09  0:47             ` Max Filippov
2019-04-03  3:43 ` [Qemu-devel] [PATCH 24/26] tcg: Use CPUClass::tlb_fill in cputlb.c Richard Henderson
2019-04-29 17:28   ` Peter Maydell
2019-05-08  6:02     ` Philippe Mathieu-Daudé
2019-04-03  3:43 ` [Qemu-devel] [PATCH 25/26] tcg: Remove CPUClass::handle_mmu_fault Richard Henderson
2019-04-29 17:29   ` Peter Maydell
2019-05-08  6:03   ` Philippe Mathieu-Daudé
2019-04-03  3:43 ` [Qemu-devel] [PATCH 26/26] tcg: Use tlb_fill probe from tlb_vaddr_to_host Richard Henderson
2019-04-29 17:41   ` Peter Maydell
2019-05-09  5:24     ` Richard Henderson
2019-05-09  8:56       ` Peter Maydell
2019-05-09 22:24         ` Richard Henderson

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