From: Michal Wajdeczko <michal.wajdeczko@intel.com>
To: intel-gfx@lists.freedesktop.org
Subject: [PATCH v3 05/19] drm/i915/guc: Update GuC boot parameters
Date: Wed, 17 Apr 2019 05:39:50 +0000 [thread overview]
Message-ID: <20190417054004.28176-6-michal.wajdeczko@intel.com> (raw)
In-Reply-To: <20190417054004.28176-1-michal.wajdeczko@intel.com>
New GuC firmwares require updated boot parameters.
v2: rebased
Signed-off-by: Michal Wajdeczko <michal.wajdeczko@intel.com>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Cc: John Spotswood <john.a.spotswood@intel.com>
Reviewed-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
---
drivers/gpu/drm/i915/intel_guc.c | 38 +++++++++-----------------
drivers/gpu/drm/i915/intel_guc_fwif.h | 39 +++++++--------------------
2 files changed, 23 insertions(+), 54 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_guc.c b/drivers/gpu/drm/i915/intel_guc.c
index 3aabfa2d9198..8c32f9d17a11 100644
--- a/drivers/gpu/drm/i915/intel_guc.c
+++ b/drivers/gpu/drm/i915/intel_guc.c
@@ -243,14 +243,7 @@ void intel_guc_fini(struct intel_guc *guc)
static u32 guc_ctl_debug_flags(struct intel_guc *guc)
{
u32 level = intel_guc_log_get_level(&guc->log);
- u32 flags;
- u32 ads;
-
- ads = intel_guc_ggtt_offset(guc, guc->ads_vma) >> PAGE_SHIFT;
- flags = ads << GUC_ADS_ADDR_SHIFT | GUC_ADS_ENABLED;
-
- if (!GUC_LOG_LEVEL_IS_ENABLED(level))
- flags |= GUC_LOG_DEFAULT_DISABLED;
+ u32 flags = 0;
if (!GUC_LOG_LEVEL_IS_VERBOSE(level))
flags |= GUC_LOG_DISABLED;
@@ -265,11 +258,7 @@ static u32 guc_ctl_feature_flags(struct intel_guc *guc)
{
u32 flags = 0;
- flags |= GUC_CTL_VCS2_ENABLED;
-
- if (USES_GUC_SUBMISSION(guc_to_i915(guc)))
- flags |= GUC_CTL_KERNEL_SUBMISSIONS;
- else
+ if (!USES_GUC_SUBMISSION(guc_to_i915(guc)))
flags |= GUC_CTL_DISABLE_SCHEDULER;
return flags;
@@ -333,6 +322,14 @@ static u32 guc_ctl_log_params_flags(struct intel_guc *guc)
return flags;
}
+static u32 guc_ctl_ads_flags(struct intel_guc *guc)
+{
+ u32 ads = intel_guc_ggtt_offset(guc, guc->ads_vma) >> PAGE_SHIFT;
+ u32 flags = ads << GUC_ADS_ADDR_SHIFT;
+
+ return flags;
+}
+
/*
* Initialise the GuC parameter block before starting the firmware
* transfer. These parameters are read by the firmware on startup
@@ -346,20 +343,11 @@ void intel_guc_init_params(struct intel_guc *guc)
memset(params, 0, sizeof(params));
- /*
- * GuC ARAT increment is 10 ns. GuC default scheduler quantum is one
- * second. This ARAR is calculated by:
- * Scheduler-Quantum-in-ns / ARAT-increment-in-ns = 1000000000 / 10
- */
- params[GUC_CTL_ARAT_HIGH] = 0;
- params[GUC_CTL_ARAT_LOW] = 100000000;
-
- params[GUC_CTL_WA] |= GUC_CTL_WA_UK_BY_DRIVER;
-
+ params[GUC_CTL_CTXINFO] = guc_ctl_ctxinfo_flags(guc);
+ params[GUC_CTL_LOG_PARAMS] = guc_ctl_log_params_flags(guc);
params[GUC_CTL_FEATURE] = guc_ctl_feature_flags(guc);
- params[GUC_CTL_LOG_PARAMS] = guc_ctl_log_params_flags(guc);
params[GUC_CTL_DEBUG] = guc_ctl_debug_flags(guc);
- params[GUC_CTL_CTXINFO] = guc_ctl_ctxinfo_flags(guc);
+ params[GUC_CTL_ADS] = guc_ctl_ads_flags(guc);
for (i = 0; i < GUC_CTL_MAX_DWORDS; i++)
DRM_DEBUG_DRIVER("param[%2d] = %#x\n", i, params[i]);
diff --git a/drivers/gpu/drm/i915/intel_guc_fwif.h b/drivers/gpu/drm/i915/intel_guc_fwif.h
index 4528e098d3a5..e18a8c0312ef 100644
--- a/drivers/gpu/drm/i915/intel_guc_fwif.h
+++ b/drivers/gpu/drm/i915/intel_guc_fwif.h
@@ -73,44 +73,28 @@
#define GUC_STAGE_DESC_ATTR_PCH BIT(6)
#define GUC_STAGE_DESC_ATTR_TERMINATED BIT(7)
-/* The guc control data is 10 DWORDs */
+/* New GuC control data */
#define GUC_CTL_CTXINFO 0
#define GUC_CTL_CTXNUM_IN16_SHIFT 0
#define GUC_CTL_BASE_ADDR_SHIFT 12
-#define GUC_CTL_ARAT_HIGH 1
-#define GUC_CTL_ARAT_LOW 2
-
-#define GUC_CTL_DEVICE_INFO 3
-
-#define GUC_CTL_LOG_PARAMS 4
+#define GUC_CTL_LOG_PARAMS 1
#define GUC_LOG_VALID (1 << 0)
#define GUC_LOG_NOTIFY_ON_HALF_FULL (1 << 1)
#define GUC_LOG_ALLOC_IN_MEGABYTE (1 << 3)
#define GUC_LOG_CRASH_SHIFT 4
-#define GUC_LOG_CRASH_MASK (0x1 << GUC_LOG_CRASH_SHIFT)
+#define GUC_LOG_CRASH_MASK (0x3 << GUC_LOG_CRASH_SHIFT)
#define GUC_LOG_DPC_SHIFT 6
#define GUC_LOG_DPC_MASK (0x7 << GUC_LOG_DPC_SHIFT)
#define GUC_LOG_ISR_SHIFT 9
#define GUC_LOG_ISR_MASK (0x7 << GUC_LOG_ISR_SHIFT)
#define GUC_LOG_BUF_ADDR_SHIFT 12
-#define GUC_CTL_PAGE_FAULT_CONTROL 5
-
-#define GUC_CTL_WA 6
-#define GUC_CTL_WA_UK_BY_DRIVER (1 << 3)
-
-#define GUC_CTL_FEATURE 7
-#define GUC_CTL_VCS2_ENABLED (1 << 0)
-#define GUC_CTL_KERNEL_SUBMISSIONS (1 << 1)
-#define GUC_CTL_FEATURE2 (1 << 2)
-#define GUC_CTL_POWER_GATING (1 << 3)
-#define GUC_CTL_DISABLE_SCHEDULER (1 << 4)
-#define GUC_CTL_PREEMPTION_LOG (1 << 5)
-#define GUC_CTL_ENABLE_SLPC (1 << 7)
-#define GUC_CTL_RESET_ON_PREMPT_FAILURE (1 << 8)
+#define GUC_CTL_WA 2
+#define GUC_CTL_FEATURE 3
+#define GUC_CTL_DISABLE_SCHEDULER (1 << 14)
-#define GUC_CTL_DEBUG 8
+#define GUC_CTL_DEBUG 4
#define GUC_LOG_VERBOSITY_SHIFT 0
#define GUC_LOG_VERBOSITY_LOW (0 << GUC_LOG_VERBOSITY_SHIFT)
#define GUC_LOG_VERBOSITY_MED (1 << GUC_LOG_VERBOSITY_SHIFT)
@@ -123,13 +107,10 @@
#define GUC_LOG_DESTINATION_MASK (3 << 4)
#define GUC_LOG_DISABLED (1 << 6)
#define GUC_PROFILE_ENABLED (1 << 7)
-#define GUC_WQ_TRACK_ENABLED (1 << 8)
-#define GUC_ADS_ENABLED (1 << 9)
-#define GUC_LOG_DEFAULT_DISABLED (1 << 10)
-#define GUC_ADS_ADDR_SHIFT 11
-#define GUC_ADS_ADDR_MASK 0xfffff800
-#define GUC_CTL_RSRVD 9
+#define GUC_CTL_ADS 5
+#define GUC_ADS_ADDR_SHIFT 1
+#define GUC_ADS_ADDR_MASK (0xFFFFF << GUC_ADS_ADDR_SHIFT)
#define GUC_CTL_MAX_DWORDS (SOFT_SCRATCH_COUNT - 2) /* [1..14] */
--
2.19.2
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next prev parent reply other threads:[~2019-04-17 5:40 UTC|newest]
Thread overview: 30+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-04-17 5:39 [PATCH v3 00/19] GuC 32.0.3 Michal Wajdeczko
2019-04-17 5:39 ` [PATCH v3 01/19] drm/i915/guc: Change platform default GuC mode Michal Wajdeczko
2019-04-18 13:59 ` Ye, Tony
2019-04-22 20:29 ` Sujaritha
2019-04-17 5:39 ` [PATCH v3 02/19] drm/i915/guc: Don't allow GuC submission Michal Wajdeczko
2019-04-17 7:14 ` Martin Peres
2019-04-17 5:39 ` [PATCH v3 03/19] drm/i915/guc: Update GuC firmware versions and names Michal Wajdeczko
2019-04-17 5:39 ` [PATCH v3 04/19] drm/i915/guc: Update GuC firmware CSS header Michal Wajdeczko
2019-04-17 17:35 ` Daniele Ceraolo Spurio
2019-04-17 5:39 ` Michal Wajdeczko [this message]
2019-04-17 5:39 ` [PATCH v3 06/19] drm/i915/guc: Update suspend/resume protocol Michal Wajdeczko
2019-04-17 5:39 ` [PATCH v3 07/19] drm/i915/guc: Update GuC sample-forcewake command Michal Wajdeczko
2019-04-17 5:39 ` [PATCH v3 08/19] drm/i915/guc: Update GuC ADS object definition Michal Wajdeczko
2019-04-17 17:37 ` Daniele Ceraolo Spurio
2019-04-17 5:39 ` [PATCH v3 09/19] drm/i915/guc: Reset GuC ADS during sanitize Michal Wajdeczko
2019-04-17 5:39 ` [PATCH v3 10/19] drm/i915/guc: Always ask GuC to update power domain states Michal Wajdeczko
2019-04-17 5:39 ` [PATCH v3 11/19] drm/i915/guc: New GuC interrupt register for Gen11 Michal Wajdeczko
2019-04-17 5:39 ` [PATCH v3 12/19] drm/i915/guc: New GuC scratch registers " Michal Wajdeczko
2019-04-17 5:39 ` [PATCH v3 13/19] drm/i915/huc: New HuC status register " Michal Wajdeczko
2019-04-17 17:39 ` Daniele Ceraolo Spurio
2019-04-17 5:39 ` [PATCH v3 14/19] drm/i915/guc: Create vfuncs for the GuC interrupts control functions Michal Wajdeczko
2019-04-17 5:40 ` [PATCH v3 15/19] drm/i915/guc: Correctly handle GuC interrupts on Gen11 Michal Wajdeczko
2019-04-17 5:40 ` [PATCH v3 16/19] drm/i915/guc: Update GuC CTB response definition Michal Wajdeczko
2019-04-17 5:40 ` [PATCH v3 17/19] drm/i915/guc: Enable GuC CTB communication on Gen11 Michal Wajdeczko
2019-04-17 5:40 ` [PATCH v3 18/19] drm/i915/guc: Define GuC firmware version for Icelake Michal Wajdeczko
2019-04-17 5:40 ` [PATCH v3 19/19] drm/i915/huc: Define HuC " Michal Wajdeczko
2019-04-17 6:32 ` ✗ Fi.CI.SPARSE: warning for GuC 32.0.3 (rev4) Patchwork
2019-04-17 6:40 ` ✓ Fi.CI.BAT: success " Patchwork
2019-04-17 13:23 ` ✓ Fi.CI.IGT: " Patchwork
2019-04-19 19:53 ` [PATCH v3 00/19] GuC 32.0.3 Chris Wilson
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