From: "Ville Syrjälä" <ville.syrjala@linux.intel.com>
To: intel-gfx@lists.freedesktop.org
Subject: Re: ✓ Fi.CI.BAT: success for series starting with [v5,1/2] drm/i915: Make sandybridge_pcode_read() deal with the second data register
Date: Wed, 22 May 2019 21:28:12 +0300 [thread overview]
Message-ID: <20190522182812.GB6464@intel.com> (raw)
In-Reply-To: <20190521183730.13175.28214@emeril.freedesktop.org>
On Tue, May 21, 2019 at 06:37:30PM -0000, Patchwork wrote:
> == Series Details ==
>
> Series: series starting with [v5,1/2] drm/i915: Make sandybridge_pcode_read() deal with the second data register
> URL : https://patchwork.freedesktop.org/series/60921/
> State : success
>
> == Summary ==
>
> CI Bug Log - changes from CI_DRM_6114 -> Patchwork_13064
> ====================================================
>
> Summary
> -------
>
> **SUCCESS**
>
> No regressions found.
>
> External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13064/
>
> Possible new issues
> -------------------
>
> Here are the unknown changes that may have been introduced in Patchwork_13064:
>
> ### IGT changes ###
>
> #### Suppressed ####
>
> The following results come from untrusted machines, tests, or statuses.
> They do not affect the overall result.
>
> * igt@i915_pm_rpm@module-reload:
> - {fi-icl-y}: [PASS][1] -> [DMESG-WARN][2] +1 similar issue
> [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6114/fi-icl-y/igt@i915_pm_rpm@module-reload.html
> [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13064/fi-icl-y/igt@i915_pm_rpm@module-reload.html
Sigh. Looks like pcode on this icl-y doesn't support the new commands
to retrieve the memory subsystem information. BIOS update maybe could
fix that?
--
Ville Syrjälä
Intel
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next prev parent reply other threads:[~2019-05-22 18:28 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-05-21 16:40 [PATCH v5 1/2] drm/i915: Make sandybridge_pcode_read() deal with the second data register Ville Syrjala
2019-05-21 16:40 ` [PATCH v5 2/2] drm/i915: Make sure we have enough memory bandwidth on ICL Ville Syrjala
2019-05-24 15:36 ` [PATCH v6 " Ville Syrjala
2019-05-27 17:55 ` Ville Syrjälä
2019-05-21 18:16 ` ✗ Fi.CI.CHECKPATCH: warning for series starting with [v5,1/2] drm/i915: Make sandybridge_pcode_read() deal with the second data register Patchwork
2019-05-21 18:18 ` ✗ Fi.CI.SPARSE: " Patchwork
2019-05-21 18:37 ` ✓ Fi.CI.BAT: success " Patchwork
2019-05-22 18:28 ` Ville Syrjälä [this message]
2019-05-22 13:15 ` ✗ Fi.CI.IGT: failure " Patchwork
2019-05-26 11:25 ` ✗ Fi.CI.CHECKPATCH: warning for series starting with [v5,1/2] drm/i915: Make sandybridge_pcode_read() deal with the second data register (rev2) Patchwork
2019-05-26 11:27 ` ✗ Fi.CI.SPARSE: " Patchwork
2019-05-26 11:42 ` ✓ Fi.CI.BAT: success " Patchwork
2019-05-26 20:09 ` ✓ Fi.CI.IGT: " Patchwork
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