Re: [PATCH v4 01/10] ata: libahci: Ensure the host interrupt status bits are cleared

From: Miquel Raynal <miquel.raynal@bootlin.com>
To: Marc Zyngier <marc.zyngier@arm.com>
Cc: Mark Rutland <mark.rutland@arm.com>, Andrew Lunn <andrew@lunn.ch>,
	raymond pang <raymondpangxd@gmail.com>,
	Jason Cooper <jason@lakedaemon.net>,
	Nadav Haklai <nadavh@marvell.com>,
	devicetree@vger.kernel.org,
	Antoine Tenart <antoine.tenart@bootlin.com>,
	Gregory Clement <gregory.clement@bootlin.com>,
	Baruch Siach <baruch@tkos.co.il>,
	Maxime Chevallier <maxime.chevallier@bootlin.com>,
	linux-ide@vger.kernel.org, Hans de Goede <hdegoede@redhat.com>,
	Rob Herring <robh+dt@kernel.org>, Jens Axboe <axboe@kernel.dk>,
	Thomas Petazzoni <thomas.petazzoni@bootlin.com>,
	Thomas Gleixner <tglx@linutronix.de>,
	linux-arm-kernel@lists.infradead.org,
	Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Subject: Re: [PATCH v4 01/10] ata: libahci: Ensure the host interrupt status bits are cleared
Date: Wed, 29 May 2019 12:08:33 +0200	[thread overview]
Message-ID: <20190529120833.29334c70@xps13> (raw)
In-Reply-To: <53ce8c5b-46fc-c969-5168-18e4bcc62cde@arm.com>

Hi Marc & Raymond,

Marc Zyngier <marc.zyngier@arm.com> wrote on Thu, 23 May 2019 10:26:01
+0100:

> On 23/05/2019 04:11, raymond pang wrote:
> > Hi Miquel,
> > 
> > This patch adds clearing GHC.IS into hot path, could you explain how
> > irq storm is generated? thanks
> > According to AHCI Spec, HBA should not refer to GHC.IS to generate
> > MSI when applying multiple MSIs.  
> 
> Well spotted.
> 
> I have the ugly feeling that this is because the Marvell AHCI
> implementation is not using MSIs at all, but instead a pair of wired
> interrupts (which are level triggered instead of edge, hence the
> screaming interrupts).
> 
> The changes in the following patches abuse the rest of the driver by
> pretending this is a a multi-MSI setup, while it clearly doesn't match
> the expectation of the AHCI spec for MSIs.
> 
> It looks like this shouldn't be imposed on other unsuspecting
> implementations which correctly use edge-triggered MSIs and do not
> require such an MMIO access.

I understand your concern, let me add a AHCI_HFLAG_LEVEL_MSI in
hpriv->flags which will be used by the mvebu_ahci.c driver to request
for this MMIO access. This way, the hot path remains the same.

Thanks,
Miquèl

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