✗ Fi.CI.CHECKPATCH: warning for Implicit dev_priv removal

From: Patchwork <patchwork@emeril.freedesktop.org>
To: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
Cc: intel-gfx@lists.freedesktop.org
Subject: ✗ Fi.CI.CHECKPATCH: warning for Implicit dev_priv removal
Date: Thu, 06 Jun 2019 10:10:40 -0000	[thread overview]
Message-ID: <20190606101040.5896.54812@emeril.freedesktop.org> (raw)
In-Reply-To: <20190606093639.9372-1-tvrtko.ursulin@linux.intel.com>

== Series Details ==

Series: Implicit dev_priv removal
URL   : https://patchwork.freedesktop.org/series/61705/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
970f22aa796e drm/i915: Reset only affected engines when handling error capture
118c531673db drm/i915: Tidy engine mask types in hangcheck
487a7e723cb2 drm/i915: Make Gen6/7 RING_FAULT_REG access engine centric
-:21: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'engine__' - possible side-effects?
#21: FILE: drivers/gpu/drm/i915/gt/intel_engine.h:71:
+#define GEN6_RING_FAULT_REG_READ(engine__) \
+	intel_uncore_read((engine__)->uncore, RING_FAULT_REG(engine__))

-:24: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'engine__' - possible side-effects?
#24: FILE: drivers/gpu/drm/i915/gt/intel_engine.h:74:
+#define GEN6_RING_FAULT_REG_POSTING_READ(engine__) \
+	intel_uncore_posting_read((engine__)->uncore, RING_FAULT_REG(engine__))

-:27: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'engine__' - possible side-effects?
#27: FILE: drivers/gpu/drm/i915/gt/intel_engine.h:77:
+#define GEN6_RING_FAULT_REG_RMW(engine__, clear__, set__) \
+({ \
+	u32 __val; \
+\
+	__val = intel_uncore_read((engine__)->uncore, \
+				  RING_FAULT_REG(engine__)); \
+	__val &= ~clear__; \
+	__val |= set__; \
+	intel_uncore_write((engine__)->uncore, RING_FAULT_REG(engine__), \
+			   __val); \
+})

-:27: CHECK:MACRO_ARG_PRECEDENCE: Macro argument 'clear__' may be better as '(clear__)' to avoid precedence issues
#27: FILE: drivers/gpu/drm/i915/gt/intel_engine.h:77:
+#define GEN6_RING_FAULT_REG_RMW(engine__, clear__, set__) \
+({ \
+	u32 __val; \
+\
+	__val = intel_uncore_read((engine__)->uncore, \
+				  RING_FAULT_REG(engine__)); \
+	__val &= ~clear__; \
+	__val |= set__; \
+	intel_uncore_write((engine__)->uncore, RING_FAULT_REG(engine__), \
+			   __val); \
+})

total: 0 errors, 0 warnings, 4 checks, 52 lines checked
dcdc5de72696 drm/i915: Extract engine fault reset to a helper
b55202be923f drm/i915: Make i915_clear_error_registers take uncore
98b9f03fb517 drm/i915: Convert some more bits to use engine mmio accessors
c2931187c171 drm/i915: Make read_subslice_reg take uncore
757bf4f8daeb drm/i915: Tidy intel_execlists_submission_init
245580be209a drm/i915: Make i915_check_and_clear_faults take uncore
edcc073dabcf drm/i915: Move scheduler caps init to i915_gem_init
182392e93cd0 drm/i915: Remove impossible path from i915_gem_init_swizzling
f6f9bb0e5889 drm/i915: Convert i915_gem_init_swizzling to uncore
9d1ee9205692 drm/i915: Convert init_unused_rings to uncore
83da7c8ed5bc drm/i915: Convert gt workarounds to uncore
b320ea58c2e1 drm/i915: Convert intel_mocs_init_l3cc_table to uncore
f0e98038c584 drm/i915: Convert i915_ppgtt_init_hw to uncore
fd20c02086dd drm/i915: Consolidate some open coded mmio rmw
6e633291b272 drm/i915: Convert i915_gem_init_hw to uncore
-:126: WARNING:AVOID_BUG: Avoid crashing the kernel - try using WARN_ON & recovery code rather than BUG() or BUG_ON()
#126: FILE: drivers/gpu/drm/i915/i915_gem.c:1337:
+	BUG_ON(!i915->kernel_context);

total: 0 errors, 1 warnings, 0 checks, 115 lines checked
e465b03ce165 drm/i915: Convert intel_vgt_(de)balloon to uncore
1cda79f98e38 drm/i915: Make GuC GGTT reservation work on ggtt
d4566f34339d drm/i915: Unexport i915_gem_init/fini_aliasing_ppgtt

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