From: Stephen Boyd <sboyd@kernel.org>
To: Vinod Koul <vkoul@kernel.org>
Cc: linux-arm-msm@vger.kernel.org,
Bjorn Andersson <bjorn.andersson@linaro.org>,
Deepak Katragadda <dkatraga@codeaurora.org>,
Andy Gross <agross@kernel.org>,
David Brown <david.brown@linaro.org>,
Michael Turquette <mturquette@baylibre.com>,
linux-clk@vger.kernel.org, Taniya Das <tdas@codeaurora.org>
Subject: Re: [PATCH 1/2] clk: qcom: clk-alpha-pll: Add support for Trion PLLs
Date: Mon, 10 Jun 2019 08:06:45 -0700 [thread overview]
Message-ID: <20190610150646.2003720859@mail.kernel.org> (raw)
In-Reply-To: <20190608091436.GF9160@vkoul-mobl.Dlink>
Quoting Vinod Koul (2019-06-08 02:14:36)
> On 07-06-19, 10:55, Stephen Boyd wrote:
> > Quoting Vinod Koul (2019-06-07 03:12:33)
>
> > > const struct clk_ops clk_alpha_pll_ops = {
> > > .enable = clk_alpha_pll_enable,
> > > .disable = clk_alpha_pll_disable,
> > > @@ -902,6 +1079,10 @@ static int alpha_pll_fabia_enable(struct clk_hw *hw)
> > > ret = regmap_read(regmap, PLL_OPMODE(pll), &opmode_val);
> > > if (ret)
> > > return ret;
> > > + ret = regmap_update_bits(regmap, PLL_MODE(pll),
> > > + PLL_BYPASSNL, PLL_BYPASSNL);
> > > + if (ret)
> > > + return ret;
> >
> > What is this?
>
> Sorry am not sure I understood the question. care to elaborate please?
The bypass bit of a PLL is very generic so I'm confused why the enable
function is only gaining this bit setting logic now. Plus, it's all
grouped together with the previous line so it looks like a possible
stray addition to the code? And after this there's an early exit from
the function if the PLL is already running, so we would put the PLL into
bypass and then return? What's going on here?
next prev parent reply other threads:[~2019-06-10 15:06 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-06-07 10:12 [PATCH 1/2] clk: qcom: clk-alpha-pll: Add support for Trion PLLs Vinod Koul
2019-06-07 10:12 ` [PATCH 2/2] clk: qcom: gcc: Add global clock controller driver for SM8150 Vinod Koul
2019-06-07 17:43 ` Stephen Boyd
2019-06-07 17:43 ` Stephen Boyd
2019-06-08 9:15 ` Vinod Koul
2019-06-10 15:08 ` Stephen Boyd
2019-06-12 5:07 ` Vinod Koul
2019-07-09 1:56 ` Rob Herring
2019-06-07 17:55 ` [PATCH 1/2] clk: qcom: clk-alpha-pll: Add support for Trion PLLs Stephen Boyd
2019-06-08 9:14 ` Vinod Koul
2019-06-10 15:06 ` Stephen Boyd [this message]
2019-06-12 5:10 ` Vinod Koul
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