From: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
To: Intel-gfx@lists.freedesktop.org
Subject: [CI 33/33] drm/i915: Eliminate dual personality of i915_scratch_offset
Date: Thu, 20 Jun 2019 21:38:35 +0100 [thread overview]
Message-ID: <20190620203835.1421-33-tvrtko.ursulin@linux.intel.com> (raw)
In-Reply-To: <20190620203835.1421-1-tvrtko.ursulin@linux.intel.com>
From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Scratch vma lives under gt but the API used to work on i915. Make this
consistent by renaming the function to intel_gt_scratch_offset and make
it take struct intel_gt.
v2:
* Move to intel_gt. (Chris)
Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
---
drivers/gpu/drm/i915/gt/intel_engine_cs.c | 2 +-
drivers/gpu/drm/i915/gt/intel_gt.c | 38 ++++++++++++++++++++++
drivers/gpu/drm/i915/gt/intel_gt.h | 8 +++++
drivers/gpu/drm/i915/gt/intel_lrc.c | 9 ++---
drivers/gpu/drm/i915/gt/intel_ringbuffer.c | 30 ++++++++++-------
drivers/gpu/drm/i915/i915_drv.h | 5 ---
drivers/gpu/drm/i915/i915_gem.c | 31 ++----------------
drivers/gpu/drm/i915/i915_gpu_error.c | 4 +--
8 files changed, 75 insertions(+), 52 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
index e30212e219ec..4961f74fd902 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
@@ -734,7 +734,7 @@ static int measure_breadcrumb_dw(struct intel_engine_cs *engine)
struct measure_breadcrumb *frame;
int dw = -ENOMEM;
- GEM_BUG_ON(!engine->i915->gt.scratch);
+ GEM_BUG_ON(!engine->gt->scratch);
frame = kzalloc(sizeof(*frame), GFP_KERNEL);
if (!frame)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c b/drivers/gpu/drm/i915/gt/intel_gt.c
index e22ee3e823fa..8cca6b22b386 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt.c
@@ -203,3 +203,41 @@ void intel_gt_chipset_flush(struct intel_gt *gt)
if (INTEL_GEN(gt->i915) < 6)
intel_gtt_chipset_flush();
}
+
+int intel_gt_init_scratch(struct intel_gt *gt, unsigned int size)
+{
+ struct drm_i915_private *i915 = gt->i915;
+ struct drm_i915_gem_object *obj;
+ struct i915_vma *vma;
+ int ret;
+
+ obj = i915_gem_object_create_stolen(i915, size);
+ if (!obj)
+ obj = i915_gem_object_create_internal(i915, size);
+ if (IS_ERR(obj)) {
+ DRM_ERROR("Failed to allocate scratch page\n");
+ return PTR_ERR(obj);
+ }
+
+ vma = i915_vma_instance(obj, >->ggtt->vm, NULL);
+ if (IS_ERR(vma)) {
+ ret = PTR_ERR(vma);
+ goto err_unref;
+ }
+
+ ret = i915_vma_pin(vma, 0, 0, PIN_GLOBAL | PIN_HIGH);
+ if (ret)
+ goto err_unref;
+
+ gt->scratch = vma;
+ return 0;
+
+err_unref:
+ i915_gem_object_put(obj);
+ return ret;
+}
+
+void intel_gt_fini_scratch(struct intel_gt *gt)
+{
+ i915_vma_unpin_and_release(>->scratch, 0);
+}
diff --git a/drivers/gpu/drm/i915/gt/intel_gt.h b/drivers/gpu/drm/i915/gt/intel_gt.h
index 29cd15be6a01..cf3c6cecc8ee 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt.h
@@ -21,4 +21,12 @@ void intel_gt_clear_error_registers(struct intel_gt *gt,
void intel_gt_flush_ggtt_writes(struct intel_gt *gt);
void intel_gt_chipset_flush(struct intel_gt *gt);
+int intel_gt_init_scratch(struct intel_gt *gt, unsigned int size);
+void intel_gt_fini_scratch(struct intel_gt *gt);
+
+static inline u32 intel_gt_scratch_offset(const struct intel_gt *gt)
+{
+ return i915_ggtt_offset(gt->scratch);
+}
+
#endif /* __INTEL_GT_H__ */
diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c
index 4fce6895e9ab..e7c8ea4e1cce 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc.c
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
@@ -135,6 +135,7 @@
#include "gem/i915_gem_context.h"
+#include "gt/intel_gt.h"
#include "i915_drv.h"
#include "i915_gem_render_state.h"
#include "i915_vgpu.h"
@@ -1756,7 +1757,7 @@ gen8_emit_flush_coherentl3_wa(struct intel_engine_cs *engine, u32 *batch)
/* NB no one else is allowed to scribble over scratch + 256! */
*batch++ = MI_STORE_REGISTER_MEM_GEN8 | MI_SRM_LRM_GLOBAL_GTT;
*batch++ = i915_mmio_reg_offset(GEN8_L3SQCREG4);
- *batch++ = i915_scratch_offset(engine->i915) + 256;
+ *batch++ = intel_gt_scratch_offset(engine->gt) + 256;
*batch++ = 0;
*batch++ = MI_LOAD_REGISTER_IMM(1);
@@ -1770,7 +1771,7 @@ gen8_emit_flush_coherentl3_wa(struct intel_engine_cs *engine, u32 *batch)
*batch++ = MI_LOAD_REGISTER_MEM_GEN8 | MI_SRM_LRM_GLOBAL_GTT;
*batch++ = i915_mmio_reg_offset(GEN8_L3SQCREG4);
- *batch++ = i915_scratch_offset(engine->i915) + 256;
+ *batch++ = intel_gt_scratch_offset(engine->gt) + 256;
*batch++ = 0;
return batch;
@@ -1807,7 +1808,7 @@ static u32 *gen8_init_indirectctx_bb(struct intel_engine_cs *engine, u32 *batch)
PIPE_CONTROL_GLOBAL_GTT_IVB |
PIPE_CONTROL_CS_STALL |
PIPE_CONTROL_QW_WRITE,
- i915_scratch_offset(engine->i915) +
+ intel_gt_scratch_offset(engine->gt) +
2 * CACHELINE_BYTES);
*batch++ = MI_ARB_ON_OFF | MI_ARB_ENABLE;
@@ -2501,7 +2502,7 @@ static int gen8_emit_flush_render(struct i915_request *request,
{
struct intel_engine_cs *engine = request->engine;
u32 scratch_addr =
- i915_scratch_offset(engine->i915) + 2 * CACHELINE_BYTES;
+ intel_gt_scratch_offset(engine->gt) + 2 * CACHELINE_BYTES;
bool vf_flush_wa = false, dc_flush_wa = false;
u32 *cs, flags = 0;
int len;
diff --git a/drivers/gpu/drm/i915/gt/intel_ringbuffer.c b/drivers/gpu/drm/i915/gt/intel_ringbuffer.c
index aa483bba04bf..d65b8cba1a8f 100644
--- a/drivers/gpu/drm/i915/gt/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/gt/intel_ringbuffer.c
@@ -33,6 +33,8 @@
#include "gem/i915_gem_context.h"
+#include "gt/intel_gt.h"
+
#include "i915_drv.h"
#include "i915_gem_render_state.h"
#include "i915_trace.h"
@@ -75,7 +77,7 @@ gen2_render_ring_flush(struct i915_request *rq, u32 mode)
*cs++ = cmd;
while (num_store_dw--) {
*cs++ = MI_STORE_DWORD_IMM | MI_MEM_VIRTUAL;
- *cs++ = i915_scratch_offset(rq->i915);
+ *cs++ = intel_gt_scratch_offset(rq->engine->gt);
*cs++ = 0;
}
*cs++ = MI_FLUSH | MI_NO_WRITE_FLUSH;
@@ -148,7 +150,8 @@ gen4_render_ring_flush(struct i915_request *rq, u32 mode)
*/
if (mode & EMIT_INVALIDATE) {
*cs++ = GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE;
- *cs++ = i915_scratch_offset(rq->i915) | PIPE_CONTROL_GLOBAL_GTT;
+ *cs++ = intel_gt_scratch_offset(rq->engine->gt) |
+ PIPE_CONTROL_GLOBAL_GTT;
*cs++ = 0;
*cs++ = 0;
@@ -156,7 +159,8 @@ gen4_render_ring_flush(struct i915_request *rq, u32 mode)
*cs++ = MI_FLUSH;
*cs++ = GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE;
- *cs++ = i915_scratch_offset(rq->i915) | PIPE_CONTROL_GLOBAL_GTT;
+ *cs++ = intel_gt_scratch_offset(rq->engine->gt) |
+ PIPE_CONTROL_GLOBAL_GTT;
*cs++ = 0;
*cs++ = 0;
}
@@ -208,7 +212,8 @@ gen4_render_ring_flush(struct i915_request *rq, u32 mode)
static int
gen6_emit_post_sync_nonzero_flush(struct i915_request *rq)
{
- u32 scratch_addr = i915_scratch_offset(rq->i915) + 2 * CACHELINE_BYTES;
+ u32 scratch_addr =
+ intel_gt_scratch_offset(rq->engine->gt) + 2 * CACHELINE_BYTES;
u32 *cs;
cs = intel_ring_begin(rq, 6);
@@ -241,7 +246,8 @@ gen6_emit_post_sync_nonzero_flush(struct i915_request *rq)
static int
gen6_render_ring_flush(struct i915_request *rq, u32 mode)
{
- u32 scratch_addr = i915_scratch_offset(rq->i915) + 2 * CACHELINE_BYTES;
+ u32 scratch_addr =
+ intel_gt_scratch_offset(rq->engine->gt) + 2 * CACHELINE_BYTES;
u32 *cs, flags = 0;
int ret;
@@ -299,7 +305,8 @@ static u32 *gen6_rcs_emit_breadcrumb(struct i915_request *rq, u32 *cs)
*cs++ = GFX_OP_PIPE_CONTROL(4);
*cs++ = PIPE_CONTROL_QW_WRITE;
- *cs++ = i915_scratch_offset(rq->i915) | PIPE_CONTROL_GLOBAL_GTT;
+ *cs++ = intel_gt_scratch_offset(rq->engine->gt) |
+ PIPE_CONTROL_GLOBAL_GTT;
*cs++ = 0;
/* Finally we can flush and with it emit the breadcrumb */
@@ -342,7 +349,8 @@ gen7_render_ring_cs_stall_wa(struct i915_request *rq)
static int
gen7_render_ring_flush(struct i915_request *rq, u32 mode)
{
- u32 scratch_addr = i915_scratch_offset(rq->i915) + 2 * CACHELINE_BYTES;
+ u32 scratch_addr =
+ intel_gt_scratch_offset(rq->engine->gt) + 2 * CACHELINE_BYTES;
u32 *cs, flags = 0;
/*
@@ -1071,9 +1079,9 @@ i830_emit_bb_start(struct i915_request *rq,
u64 offset, u32 len,
unsigned int dispatch_flags)
{
- u32 *cs, cs_offset = i915_scratch_offset(rq->i915);
+ u32 *cs, cs_offset = intel_gt_scratch_offset(rq->engine->gt);
- GEM_BUG_ON(rq->i915->gt.scratch->size < I830_WA_SIZE);
+ GEM_BUG_ON(rq->engine->gt->scratch->size < I830_WA_SIZE);
cs = intel_ring_begin(rq, 6);
if (IS_ERR(cs))
@@ -1513,7 +1521,7 @@ static int flush_pd_dir(struct i915_request *rq)
/* Stall until the page table load is complete */
*cs++ = MI_STORE_REGISTER_MEM | MI_SRM_LRM_GLOBAL_GTT;
*cs++ = i915_mmio_reg_offset(RING_PP_DIR_BASE(engine->mmio_base));
- *cs++ = i915_scratch_offset(rq->i915);
+ *cs++ = intel_gt_scratch_offset(rq->engine->gt);
*cs++ = MI_NOOP;
intel_ring_advance(rq, cs);
@@ -1629,7 +1637,7 @@ static inline int mi_set_context(struct i915_request *rq, u32 flags)
/* Insert a delay before the next switch! */
*cs++ = MI_STORE_REGISTER_MEM | MI_SRM_LRM_GLOBAL_GTT;
*cs++ = i915_mmio_reg_offset(last_reg);
- *cs++ = i915_scratch_offset(rq->i915);
+ *cs++ = intel_gt_scratch_offset(rq->engine->gt);
*cs++ = MI_NOOP;
}
*cs++ = MI_ARB_ON_OFF | MI_ARB_ENABLE;
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 89a21fa4eac2..4077d15fe429 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2783,11 +2783,6 @@ static inline int intel_hws_csb_write_index(struct drm_i915_private *i915)
return I915_HWS_CSB_WRITE_INDEX;
}
-static inline u32 i915_scratch_offset(const struct drm_i915_private *i915)
-{
- return i915_ggtt_offset(i915->gt.scratch);
-}
-
static inline enum i915_map_type
i915_coherent_map_type(struct drm_i915_private *i915)
{
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 6e07127242d9..8dff3b8f12c3 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -1424,39 +1424,12 @@ static int __intel_engines_record_defaults(struct drm_i915_private *i915)
static int
i915_gem_init_scratch(struct drm_i915_private *i915, unsigned int size)
{
- struct drm_i915_gem_object *obj;
- struct i915_vma *vma;
- int ret;
-
- obj = i915_gem_object_create_stolen(i915, size);
- if (!obj)
- obj = i915_gem_object_create_internal(i915, size);
- if (IS_ERR(obj)) {
- DRM_ERROR("Failed to allocate scratch page\n");
- return PTR_ERR(obj);
- }
-
- vma = i915_vma_instance(obj, &i915->ggtt.vm, NULL);
- if (IS_ERR(vma)) {
- ret = PTR_ERR(vma);
- goto err_unref;
- }
-
- ret = i915_vma_pin(vma, 0, 0, PIN_GLOBAL | PIN_HIGH);
- if (ret)
- goto err_unref;
-
- i915->gt.scratch = vma;
- return 0;
-
-err_unref:
- i915_gem_object_put(obj);
- return ret;
+ return intel_gt_init_scratch(&i915->gt, size);
}
static void i915_gem_fini_scratch(struct drm_i915_private *i915)
{
- i915_vma_unpin_and_release(&i915->gt.scratch, 0);
+ intel_gt_fini_scratch(&i915->gt);
}
static int intel_engines_verify_workarounds(struct drm_i915_private *i915)
diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c b/drivers/gpu/drm/i915/i915_gpu_error.c
index 330a25c5db6a..59f5b0265ee3 100644
--- a/drivers/gpu/drm/i915/i915_gpu_error.c
+++ b/drivers/gpu/drm/i915/i915_gpu_error.c
@@ -1441,8 +1441,8 @@ static void gem_record_rings(struct i915_gpu_state *error)
if (HAS_BROKEN_CS_TLB(i915))
ee->wa_batchbuffer =
- i915_error_object_create(i915,
- i915->gt.scratch);
+ i915_error_object_create(i915,
+ engine->gt->scratch);
request_record_user_bo(request, ee);
ee->ctx =
--
2.20.1
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next prev parent reply other threads:[~2019-06-20 20:39 UTC|newest]
Thread overview: 36+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-06-20 20:38 [CI 01/33] drm/i915: Convert intel_vgt_(de)balloon to uncore Tvrtko Ursulin
2019-06-20 20:38 ` [CI 02/33] drm/i915: Introduce struct intel_gt as replacement for anonymous i915->gt Tvrtko Ursulin
2019-06-20 20:38 ` [CI 03/33] drm/i915: Move intel_gt initialization to a separate file Tvrtko Ursulin
2019-06-20 20:38 ` [CI 04/33] drm/i915: Store some backpointers in struct intel_gt Tvrtko Ursulin
2019-06-20 20:38 ` [CI 05/33] drm/i915: Move intel_gt_pm_init under intel_gt_init_early Tvrtko Ursulin
2019-06-20 20:38 ` [CI 06/33] drm/i915: Make i915_check_and_clear_faults take intel_gt Tvrtko Ursulin
2019-06-20 20:38 ` [CI 07/33] drm/i915: Convert i915_gem_init_swizzling to intel_gt Tvrtko Ursulin
2019-06-20 20:38 ` [CI 08/33] drm/i915: Use intel_uncore_rmw in intel_gt_init_swizzling Tvrtko Ursulin
2019-06-20 20:38 ` [CI 09/33] drm/i915: Convert init_unused_rings to intel_gt Tvrtko Ursulin
2019-06-20 20:38 ` [CI 10/33] drm/i915: Convert gt workarounds " Tvrtko Ursulin
2019-06-20 20:38 ` [CI 11/33] drm/i915: Store backpointer to intel_gt in the engine Tvrtko Ursulin
2019-06-20 20:38 ` [CI 12/33] drm/i915: Convert intel_mocs_init_l3cc_table to intel_gt Tvrtko Ursulin
2019-06-20 20:38 ` [CI 13/33] drm/i915: Convert i915_ppgtt_init_hw " Tvrtko Ursulin
2019-06-20 20:38 ` [CI 14/33] drm/i915: Consolidate some open coded mmio rmw Tvrtko Ursulin
2019-06-20 20:38 ` [CI 15/33] drm/i915: Convert i915_gem_init_hw to intel_gt Tvrtko Ursulin
2019-06-20 20:38 ` [CI 16/33] drm/i915: Move intel_engines_resume into common init Tvrtko Ursulin
2019-06-20 20:38 ` [CI 17/33] drm/i915: Stop using I915_READ/WRITE in intel_wopcm_init_hw Tvrtko Ursulin
2019-06-20 20:38 ` [CI 18/33] drm/i915: Compartmentalize i915_ggtt_probe_hw Tvrtko Ursulin
2019-06-20 20:38 ` [CI 19/33] drm/i915: Compartmentalize i915_ggtt_init_hw Tvrtko Ursulin
2019-06-20 20:38 ` [CI 20/33] drm/i915: Make ggtt invalidation work on ggtt Tvrtko Ursulin
2019-06-20 20:38 ` [CI 21/33] drm/i915: Store intel_gt backpointer in vm Tvrtko Ursulin
2019-06-20 20:38 ` [CI 22/33] drm/i915: Compartmentalize i915_gem_suspend/restore_gtt_mappings Tvrtko Ursulin
2019-06-20 20:38 ` [CI 23/33] drm/i915: Convert i915_gem_flush_ggtt_writes to intel_gt Tvrtko Ursulin
2019-06-20 20:38 ` [CI 24/33] drm/i915: Move i915_gem_chipset_flush " Tvrtko Ursulin
2019-06-20 20:38 ` [CI 25/33] drm/i915: Compartmentalize timeline_init/park/fini Tvrtko Ursulin
2019-06-20 20:38 ` [CI 26/33] drm/i915: Compartmentalize i915_ggtt_cleanup_hw Tvrtko Ursulin
2019-06-20 20:38 ` [CI 27/33] drm/i915: Compartmentalize i915_gem_init_ggtt Tvrtko Ursulin
2019-06-20 20:38 ` [CI 28/33] drm/i915: Store ggtt pointer in intel_gt Tvrtko Ursulin
2019-06-20 20:38 ` [CI 29/33] drm/i915: Compartmentalize ring buffer creation Tvrtko Ursulin
2019-06-20 20:38 ` [CI 30/33] drm/i915: Save trip via top-level i915 in a few more places Tvrtko Ursulin
2019-06-20 20:38 ` [CI 31/33] drm/i915: Make timelines gt centric Tvrtko Ursulin
2019-06-20 20:38 ` [CI 32/33] drm/i915: Rename i915_timeline to intel_timeline and move under gt Tvrtko Ursulin
2019-06-20 20:38 ` Tvrtko Ursulin [this message]
2019-06-20 23:00 ` ✗ Fi.CI.BAT: failure for series starting with [CI,01/33] drm/i915: Convert intel_vgt_(de)balloon to uncore Patchwork
-- strict thread matches above, loose matches on Subject: below --
2019-06-21 7:07 [CI 01/33] " Tvrtko Ursulin
2019-06-21 7:08 ` [CI 33/33] drm/i915: Eliminate dual personality of i915_scratch_offset Tvrtko Ursulin
2019-06-19 21:34 [CI 01/33] drm/i915: Convert intel_vgt_(de)balloon to uncore Tvrtko Ursulin
2019-06-19 21:34 ` [CI 33/33] drm/i915: Eliminate dual personality of i915_scratch_offset Tvrtko Ursulin
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