From: Imre Deak <imre.deak@intel.com>
To: intel-gfx@lists.freedesktop.org
Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
Subject: [PATCH v3 04/23] drm/i915: Sanitize the terminology used for TypeC port modes
Date: Fri, 28 Jun 2019 17:36:16 +0300 [thread overview]
Message-ID: <20190628143635.22066-5-imre.deak@intel.com> (raw)
In-Reply-To: <20190628143635.22066-1-imre.deak@intel.com>
The TypeC port mode can switch dynamically, to reflect that better call
the port's mode as 'mode' rather than 'type'.
While at it:
- s/TC_PORT_TBT/TC_PORT_TBT_ALT/ and s/TC_PORT_TYPEC/TC_PORT_DP_ALT/.
'TYPEC' is ambiguous, TBT_ALT and DP_ALT better match the reality.
- Remove the 'unknown' TypeC port mode. The mode is always known, it's
the TBT-alt/safe mode after HW reset and after disconnecting the PHY.
Simplify the tc_port/tc_type checks accordingly.
- Don't WARN if the port mode changes, that can happen normally.
No functional changes.
Cc: Animesh Manna <animesh.manna@intel.com>
Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
Cc: José Roberto de Souza <jose.souza@intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
drivers/gpu/drm/i915/display/intel_ddi.c | 11 ++---
drivers/gpu/drm/i915/display/intel_display.h | 7 ++-
drivers/gpu/drm/i915/display/intel_dp.c | 2 +-
drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 2 +-
drivers/gpu/drm/i915/display/intel_tc.c | 48 ++++++++-----------
drivers/gpu/drm/i915/intel_drv.h | 2 +-
6 files changed, 31 insertions(+), 41 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index d06f121281ef..442cd3997109 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -2999,14 +2999,14 @@ static void icl_program_mg_dp_mode(struct intel_digital_port *intel_dig_port)
enum tc_port tc_port = intel_port_to_tc(dev_priv, port);
u32 ln0, ln1, lane_info;
- if (tc_port == PORT_TC_NONE || intel_dig_port->tc_type == TC_PORT_TBT)
+ if (intel_dig_port->tc_mode == TC_PORT_TBT_ALT)
return;
ln0 = I915_READ(MG_DP_MODE(0, port));
ln1 = I915_READ(MG_DP_MODE(1, port));
- switch (intel_dig_port->tc_type) {
- case TC_PORT_TYPEC:
+ switch (intel_dig_port->tc_mode) {
+ case TC_PORT_DP_ALT:
ln0 &= ~(MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X2_MODE);
ln1 &= ~(MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X2_MODE);
@@ -3049,7 +3049,7 @@ static void icl_program_mg_dp_mode(struct intel_digital_port *intel_dig_port)
break;
default:
- MISSING_CASE(intel_dig_port->tc_type);
+ MISSING_CASE(intel_dig_port->tc_mode);
return;
}
@@ -3643,8 +3643,7 @@ intel_ddi_pre_pll_enable(struct intel_encoder *encoder,
* Program the lane count for static/dynamic connections on Type-C ports.
* Skip this step for TBT.
*/
- if (dig_port->tc_type == TC_PORT_UNKNOWN ||
- dig_port->tc_type == TC_PORT_TBT)
+ if (dig_port->tc_mode == TC_PORT_TBT_ALT)
return;
intel_ddi_set_fia_lane_count(encoder, crtc_state, port);
diff --git a/drivers/gpu/drm/i915/display/intel_display.h b/drivers/gpu/drm/i915/display/intel_display.h
index ee6b8194a459..d296556ed82e 100644
--- a/drivers/gpu/drm/i915/display/intel_display.h
+++ b/drivers/gpu/drm/i915/display/intel_display.h
@@ -189,10 +189,9 @@ enum tc_port {
I915_MAX_TC_PORTS
};
-enum tc_port_type {
- TC_PORT_UNKNOWN = 0,
- TC_PORT_TYPEC,
- TC_PORT_TBT,
+enum tc_port_mode {
+ TC_PORT_TBT_ALT,
+ TC_PORT_DP_ALT,
TC_PORT_LEGACY,
};
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 348c70b75403..0c6afec78f93 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -1176,7 +1176,7 @@ static u32 skl_get_aux_send_ctl(struct intel_dp *intel_dp,
DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL(32) |
DP_AUX_CH_CTL_SYNC_PULSE_SKL(32);
- if (intel_dig_port->tc_type == TC_PORT_TBT)
+ if (intel_dig_port->tc_mode == TC_PORT_TBT_ALT)
ret |= DP_AUX_CH_CTL_TBT_IO;
return ret;
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index 2d4e7b9a7b9d..bf66261c8bf0 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -2817,7 +2817,7 @@ icl_get_dpll(struct intel_crtc_state *crtc_state,
intel_dig_port = enc_to_dig_port(&encoder->base);
}
- if (intel_dig_port->tc_type == TC_PORT_TBT) {
+ if (intel_dig_port->tc_mode == TC_PORT_TBT_ALT) {
min = DPLL_ID_ICL_TBTPLL;
max = min;
ret = icl_calc_dpll_state(crtc_state, encoder);
diff --git a/drivers/gpu/drm/i915/display/intel_tc.c b/drivers/gpu/drm/i915/display/intel_tc.c
index 4fa9ea695d51..59aad3e49f93 100644
--- a/drivers/gpu/drm/i915/display/intel_tc.c
+++ b/drivers/gpu/drm/i915/display/intel_tc.c
@@ -7,19 +7,18 @@
#include "i915_drv.h"
#include "intel_tc.h"
-static const char *tc_type_name(enum tc_port_type type)
+static const char *tc_port_mode_name(enum tc_port_mode mode)
{
static const char * const names[] = {
- [TC_PORT_UNKNOWN] = "unknown",
+ [TC_PORT_TBT_ALT] = "tbt-alt",
+ [TC_PORT_DP_ALT] = "dp-alt",
[TC_PORT_LEGACY] = "legacy",
- [TC_PORT_TYPEC] = "typec",
- [TC_PORT_TBT] = "tbt",
};
- if (WARN_ON(type >= ARRAY_SIZE(names)))
- type = TC_PORT_UNKNOWN;
+ if (WARN_ON(mode >= ARRAY_SIZE(names)))
+ mode = TC_PORT_TBT_ALT;
- return names[type];
+ return names[mode];
}
int intel_tc_port_fia_max_lane_count(struct intel_digital_port *dig_port)
@@ -29,7 +28,7 @@ int intel_tc_port_fia_max_lane_count(struct intel_digital_port *dig_port)
intel_wakeref_t wakeref;
u32 lane_info;
- if (tc_port == PORT_TC_NONE || dig_port->tc_type != TC_PORT_TYPEC)
+ if (dig_port->tc_mode != TC_PORT_DP_ALT)
return 4;
lane_info = 0;
@@ -81,8 +80,8 @@ static bool icl_tc_phy_connect(struct intel_digital_port *dig_port)
enum tc_port tc_port = intel_port_to_tc(dev_priv, dig_port->base.port);
u32 val;
- if (dig_port->tc_type != TC_PORT_LEGACY &&
- dig_port->tc_type != TC_PORT_TYPEC)
+ if (dig_port->tc_mode != TC_PORT_LEGACY &&
+ dig_port->tc_mode != TC_PORT_DP_ALT)
return true;
val = I915_READ(PORT_TX_DFLEXDPPMS);
@@ -106,7 +105,7 @@ static bool icl_tc_phy_connect(struct intel_digital_port *dig_port)
* Now we have to re-check the live state, in case the port recently
* became disconnected. Not necessary for legacy mode.
*/
- if (dig_port->tc_type == TC_PORT_TYPEC &&
+ if (dig_port->tc_mode == TC_PORT_DP_ALT &&
!(I915_READ(PORT_TX_DFLEXDPSP) & TC_LIVE_STATE_TC(tc_port))) {
DRM_DEBUG_KMS("TC PHY %d sudden disconnect.\n", tc_port);
icl_tc_phy_disconnect(dig_port);
@@ -125,15 +124,12 @@ void icl_tc_phy_disconnect(struct intel_digital_port *dig_port)
struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
enum tc_port tc_port = intel_port_to_tc(dev_priv, dig_port->base.port);
- if (dig_port->tc_type == TC_PORT_UNKNOWN)
- return;
-
/*
* TBT disconnection flow is read the live status, what was done in
* caller.
*/
- if (dig_port->tc_type == TC_PORT_TYPEC ||
- dig_port->tc_type == TC_PORT_LEGACY) {
+ if (dig_port->tc_mode == TC_PORT_DP_ALT ||
+ dig_port->tc_mode == TC_PORT_LEGACY) {
u32 val;
val = I915_READ(PORT_TX_DFLEXDPCSSS);
@@ -143,9 +139,9 @@ void icl_tc_phy_disconnect(struct intel_digital_port *dig_port)
DRM_DEBUG_KMS("Port %c TC type %s disconnected\n",
port_name(dig_port->base.port),
- tc_type_name(dig_port->tc_type));
+ tc_port_mode_name(dig_port->tc_mode));
- dig_port->tc_type = TC_PORT_UNKNOWN;
+ dig_port->tc_mode = TC_PORT_TBT_ALT;
}
static void icl_update_tc_port_type(struct drm_i915_private *dev_priv,
@@ -153,26 +149,22 @@ static void icl_update_tc_port_type(struct drm_i915_private *dev_priv,
bool is_legacy, bool is_typec, bool is_tbt)
{
enum port port = intel_dig_port->base.port;
- enum tc_port_type old_type = intel_dig_port->tc_type;
+ enum tc_port_mode old_mode = intel_dig_port->tc_mode;
WARN_ON(is_legacy + is_typec + is_tbt != 1);
if (is_legacy)
- intel_dig_port->tc_type = TC_PORT_LEGACY;
+ intel_dig_port->tc_mode = TC_PORT_LEGACY;
else if (is_typec)
- intel_dig_port->tc_type = TC_PORT_TYPEC;
+ intel_dig_port->tc_mode = TC_PORT_DP_ALT;
else if (is_tbt)
- intel_dig_port->tc_type = TC_PORT_TBT;
+ intel_dig_port->tc_mode = TC_PORT_TBT_ALT;
else
return;
- /* Types are not supposed to be changed at runtime. */
- WARN_ON(old_type != TC_PORT_UNKNOWN &&
- old_type != intel_dig_port->tc_type);
-
- if (old_type != intel_dig_port->tc_type)
+ if (old_mode != intel_dig_port->tc_mode)
DRM_DEBUG_KMS("Port %c has TC type %s\n", port_name(port),
- tc_type_name(intel_dig_port->tc_type));
+ tc_port_mode_name(intel_dig_port->tc_mode));
}
/*
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 1d58f7ec5d84..7159f709a7f2 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1225,7 +1225,7 @@ struct intel_digital_port {
enum aux_ch aux_ch;
enum intel_display_power_domain ddi_io_power_domain;
bool tc_legacy_port:1;
- enum tc_port_type tc_type;
+ enum tc_port_mode tc_mode;
void (*write_infoframe)(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state,
--
2.17.1
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next prev parent reply other threads:[~2019-06-28 14:36 UTC|newest]
Thread overview: 29+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-06-28 14:36 [PATCH v3 00/23] drm/i915: Fix TypeC port mode switching Imre Deak
2019-06-28 14:36 ` [PATCH v3 01/23] drm/i915/icl: Add support to read out the TBT PLL HW state Imre Deak
2019-06-28 14:36 ` [PATCH v3 02/23] drm/i915: Tune down WARNs about TBT AUX power well enabling Imre Deak
2019-06-28 14:36 ` [PATCH v3 03/23] drm/i915: Move the TypeC port handling code to a separate file Imre Deak
2019-06-28 14:36 ` Imre Deak [this message]
2019-06-28 14:36 ` [PATCH v3 05/23] drm/i915: Don't enable the DDI-IO power in the TypeC TBT-alt mode Imre Deak
2019-06-28 14:36 ` [PATCH v3 06/23] drm/i915: Fix the TBT AUX power well enabling Imre Deak
2019-06-28 14:36 ` [PATCH v3 07/23] drm/i915: Use the correct AUX power domain in TypeC TBT-alt mode Imre Deak
2019-06-28 14:36 ` [PATCH v3 08/23] drm/i915: Unify the TypeC port notation in debug/error messages Imre Deak
2019-06-28 14:36 ` [PATCH v3 09/23] drm/i915: Factor out common parts from TypeC port handling functions Imre Deak
2019-06-28 14:36 ` [PATCH v3 10/23] drm/i915: Wait for TypeC PHY complete flag to clear in safe mode Imre Deak
2019-06-28 14:36 ` [PATCH v3 11/23] drm/i915: Handle the TCCOLD power-down event Imre Deak
2019-06-28 14:36 ` [PATCH v3 12/23] drm/i915: Sanitize the TypeC connect/detect sequences Imre Deak
2019-06-28 14:36 ` [PATCH v3 13/23] drm/i915: Fix the TypeC port mode sanitization during loading/resume Imre Deak
2019-06-28 14:36 ` [PATCH v3 14/23] drm/i915: Keep the TypeC port mode fixed for detect/AUX transfers Imre Deak
2019-06-28 14:36 ` [PATCH v3 15/23] drm/i915: Sanitize the TypeC FIA lane configuration decoding Imre Deak
2019-06-28 14:36 ` [PATCH v3 16/23] drm/i915: Sanitize the shared DPLL reserve/release interface Imre Deak
2019-06-28 14:36 ` [PATCH v3 17/23] drm/i915: Sanitize the shared DPLL find/reference interface Imre Deak
2019-06-28 14:36 ` [PATCH v3 18/23] drm/i915/icl: Split getting the DPLLs to port type specific functions Imre Deak
2019-06-28 14:36 ` [PATCH v3 19/23] drm/i915/icl: Reserve all required PLLs for TypeC ports Imre Deak
2019-06-28 14:36 ` [PATCH v3 20/23] drm/i915: Keep the TypeC port mode fixed when the port is active Imre Deak
2019-06-28 14:36 ` [PATCH v3 21/23] drm/i915: Add state verification for the TypeC port mode Imre Deak
2019-06-28 14:36 ` [PATCH v3 22/23] drm/i915: Remove unneeded disconnect in TypeC legacy " Imre Deak
2019-06-28 14:36 ` [PATCH v3 23/23] drm/i915: WARN about invalid lane reversal in TBT-alt/DP-alt modes Imre Deak
2019-06-28 14:54 ` ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Fix TypeC port mode switching (rev8) Patchwork
2019-06-28 15:02 ` ✗ Fi.CI.SPARSE: " Patchwork
2019-06-28 19:04 ` ✓ Fi.CI.BAT: success " Patchwork
2019-06-29 7:03 ` ✓ Fi.CI.IGT: " Patchwork
2019-07-01 13:34 ` Imre Deak
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