From: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
To: Intel-gfx@lists.freedesktop.org
Subject: [PATCH 4/4] drm/i915/icl: Verify engine workarounds in GEN8_L3SQCREG4
Date: Tue, 9 Jul 2019 22:06:20 +0100 [thread overview]
Message-ID: <20190709210620.15805-5-tvrtko.ursulin@linux.intel.com> (raw)
In-Reply-To: <20190709210620.15805-1-tvrtko.ursulin@linux.intel.com>
From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Having fixed the incorect MCR programming in an earlier patch, we can now
stop ignoring read back of GEN8_L3SQCREG4 during engine workaround
verification.
Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
---
drivers/gpu/drm/i915/gt/intel_workarounds.c | 27 +++++----------------
1 file changed, 6 insertions(+), 21 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index b5f19ad48d22..0fa43ff7366c 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -176,19 +176,6 @@ wa_write_or(struct i915_wa_list *wal, i915_reg_t reg, u32 val)
wa_write_masked_or(wal, reg, val, val);
}
-static void
-ignore_wa_write_or(struct i915_wa_list *wal, i915_reg_t reg, u32 mask, u32 val)
-{
- struct i915_wa wa = {
- .reg = reg,
- .mask = mask,
- .val = val,
- /* Bonkers HW, skip verifying */
- };
-
- _wa_add(wal, &wa);
-}
-
#define WA_SET_BIT_MASKED(addr, mask) \
wa_write_masked_or(wal, (addr), (mask), _MASKED_BIT_ENABLE(mask))
@@ -1234,10 +1221,9 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
_3D_CHICKEN3_AA_LINE_QUALITY_FIX_ENABLE);
/* WaPipelineFlushCoherentLines:icl */
- ignore_wa_write_or(wal,
- GEN8_L3SQCREG4,
- GEN8_LQSC_FLUSH_COHERENT_LINES,
- GEN8_LQSC_FLUSH_COHERENT_LINES);
+ wa_write_or(wal,
+ GEN8_L3SQCREG4,
+ GEN8_LQSC_FLUSH_COHERENT_LINES);
/*
* Wa_1405543622:icl
@@ -1264,10 +1250,9 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
* Wa_1405733216:icl
* Formerly known as WaDisableCleanEvicts
*/
- ignore_wa_write_or(wal,
- GEN8_L3SQCREG4,
- GEN11_LQSC_CLEAN_EVICT_DISABLE,
- GEN11_LQSC_CLEAN_EVICT_DISABLE);
+ wa_write_or(wal,
+ GEN8_L3SQCREG4,
+ GEN11_LQSC_CLEAN_EVICT_DISABLE);
/* WaForwardProgressSoftReset:icl */
wa_write_or(wal,
--
2.20.1
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next prev parent reply other threads:[~2019-07-09 21:06 UTC|newest]
Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-07-09 21:06 [PATCH 0/4] MCR fixes Tvrtko Ursulin
2019-07-09 21:06 ` [PATCH 1/4] drm/i915: Fix GEN8_MCR_SELECTOR programming Tvrtko Ursulin
2019-07-09 21:09 ` Chris Wilson
2019-07-10 6:21 ` Tvrtko Ursulin
2019-07-09 21:06 ` [PATCH 2/4] drm/i915: Fix WaProgramMgsrForL3BankSpecificMmioReads Tvrtko Ursulin
2019-07-09 21:11 ` Chris Wilson
2019-07-11 9:15 ` Tvrtko Ursulin
2019-07-11 15:59 ` [PATCH v2 " Tvrtko Ursulin
2019-07-11 23:51 ` Summers, Stuart
2019-07-12 5:32 ` Tvrtko Ursulin
2019-07-09 21:06 ` [PATCH 3/4] drm/i915: Move intel_calculate_mcr_s_ss_select to intel_sseu.c Tvrtko Ursulin
2019-07-09 21:12 ` Chris Wilson
2019-07-09 21:06 ` Tvrtko Ursulin [this message]
2019-07-09 21:12 ` [PATCH 4/4] drm/i915/icl: Verify engine workarounds in GEN8_L3SQCREG4 Chris Wilson
2019-07-09 22:18 ` ✓ Fi.CI.BAT: success for MCR fixes Patchwork
2019-07-11 8:53 ` ✓ Fi.CI.IGT: " Patchwork
2019-07-11 19:05 ` ✓ Fi.CI.BAT: success for MCR fixes (rev2) Patchwork
2019-07-12 22:17 ` ✗ Fi.CI.IGT: failure " Patchwork
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