From: Anshuman Gupta <anshuman.gupta@intel.com>
To: intel-gfx@lists.freedesktop.org
Cc: Deak@freedesktop.org, jani.nikula@intel.com,
Nikula@freedesktop.org, Manna@freedesktop.org
Subject: [PATCH v3 6/9] drm/i915/tgl: Add VIDEO power domain
Date: Tue, 30 Jul 2019 19:20:21 +0530 [thread overview]
Message-ID: <20190730135024.31765-7-anshuman.gupta@intel.com> (raw)
In-Reply-To: <20190730135024.31765-1-anshuman.gupta@intel.com>
POWER_DOMAIN_VIDEO is a hook to "DC5 Off" power well,
which can disallow DC5/6 and allow DC3CO.
It will be used when there will be PSR2 idle frame while active
video playback.
Cc: Nikula, Jani <jani.nikula@intel.com>
Cc: Deak, Imre <imre.deak@intel.com>
Cc: Manna, Animesh <animesh.manna@intel.com>
Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
---
drivers/gpu/drm/i915/display/intel_display_power.c | 3 +++
drivers/gpu/drm/i915/display/intel_display_power.h | 1 +
drivers/gpu/drm/i915/i915_drv.h | 6 ++++++
3 files changed, 10 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
index c44b3c54cbcb..24df21e86a38 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -122,6 +122,8 @@ intel_display_power_domain_str(struct drm_i915_private *i915,
return "VGA";
case POWER_DOMAIN_AUDIO:
return "AUDIO";
+ case POWER_DOMAIN_VIDEO:
+ return "VIDEO";
case POWER_DOMAIN_AUX_A:
return "AUX_A";
case POWER_DOMAIN_AUX_B:
@@ -2774,6 +2776,7 @@ void intel_display_power_put(struct drm_i915_private *dev_priv,
#define TGL_DISPLAY_DC_OFF_POWER_DOMAINS ( \
TGL_PW_2_POWER_DOMAINS | \
+ BIT_ULL(POWER_DOMAIN_VIDEO) | \
BIT_ULL(POWER_DOMAIN_MODESET) | \
BIT_ULL(POWER_DOMAIN_AUX_A) | \
BIT_ULL(POWER_DOMAIN_INIT))
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.h b/drivers/gpu/drm/i915/display/intel_display_power.h
index 7a61cab1eb31..1dd221c4bee1 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.h
+++ b/drivers/gpu/drm/i915/display/intel_display_power.h
@@ -66,6 +66,7 @@ enum intel_display_power_domain {
POWER_DOMAIN_PORT_OTHER,
POWER_DOMAIN_VGA,
POWER_DOMAIN_AUDIO,
+ POWER_DOMAIN_VIDEO,
POWER_DOMAIN_AUX_A,
POWER_DOMAIN_AUX_B,
POWER_DOMAIN_AUX_C,
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 04e454e51a5e..8b7dbaa91a0d 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -361,6 +361,12 @@ struct intel_csr {
u32 allowed_dc_mask;
intel_wakeref_t wakeref;
bool prefer_dc3co;
+ intel_wakeref_t dc5_wakeref;
+ /*
+ * Mutex to protect dc5_wakeref which make maintain proper
+ * power domain reference count of POWER_DOMAIN_VIDEO
+ */
+ struct mutex dc5_mutex;
};
enum i915_cache_level {
--
2.21.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
next prev parent reply other threads:[~2019-07-30 13:54 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-07-30 13:50 [PATCH v3 0/9] DC3CO Support for TGL Anshuman Gupta
2019-07-30 13:50 ` [PATCH v3 1/9] drm/i915/tgl: Add DC3CO required register and bits Anshuman Gupta
2019-08-01 4:23 ` Animesh Manna
2019-07-30 13:50 ` [PATCH v3 2/9] drm/i915/tgl: Add DC3CO mask to allowed_dc_mask and gen9_dc_mask Anshuman Gupta
2019-08-01 4:35 ` Animesh Manna
2019-07-30 13:50 ` [PATCH v3 3/9] drm/i915/tgl: Add power well to enable DC3CO state Anshuman Gupta
2019-07-30 13:50 ` [PATCH v3 4/9] drm/i915/tgl: mutual exclusive handling for DC3CO and DC5/6 Anshuman Gupta
2019-07-30 13:50 ` [PATCH v3 5/9] drm/i915/tgl: Add helper function to prefer dc3co over dc5 Anshuman Gupta
2019-07-30 13:50 ` Anshuman Gupta [this message]
2019-07-30 13:50 ` [PATCH v3 7/9] drm/i915/tgl: DC3CO PSR2 helper Anshuman Gupta
2019-07-31 7:11 ` kbuild test robot
2019-07-30 13:50 ` [PATCH v3 8/9] drm/i915/tgl: switch between dc3co and dc5 based on display idleness Anshuman Gupta
2019-07-30 13:50 ` [PATCH v3 9/9] drm/i915/tgl: Add DC3CO counter in i915_dmc_info Anshuman Gupta
2019-07-30 14:23 ` ✗ Fi.CI.SPARSE: warning for DC3CO Support for TGL Patchwork
2019-07-30 14:41 ` ✓ Fi.CI.BAT: success " Patchwork
2019-07-31 0:37 ` ✓ Fi.CI.IGT: " Patchwork
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20190730135024.31765-7-anshuman.gupta@intel.com \
--to=anshuman.gupta@intel.com \
--cc=Deak@freedesktop.org \
--cc=Manna@freedesktop.org \
--cc=Nikula@freedesktop.org \
--cc=intel-gfx@lists.freedesktop.org \
--cc=jani.nikula@intel.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.