From: Lucas De Marchi <lucas.demarchi@intel.com>
To: intel-gfx@lists.freedesktop.org
Subject: [PATCH v2 24/40] drm/i915/tgl: move DP_TP_* to transcoder
Date: Sat, 17 Aug 2019 02:38:46 -0700 [thread overview]
Message-ID: <20190817093902.2171-25-lucas.demarchi@intel.com> (raw)
In-Reply-To: <20190817093902.2171-1-lucas.demarchi@intel.com>
Gen 12 onwards moves the DP_TP_* registers to be transcoder-based rather
than port-based. This add the new register address and changes the
functions that are used with DDI on gen 12 to use the new registers. On
MST the master transcoder is the one to be used.
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: José Roberto de Souza <jose.souza@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
drivers/gpu/drm/i915/display/intel_ddi.c | 42 ++++++++----
.../drm/i915/display/intel_display_types.h | 1 +
drivers/gpu/drm/i915/display/intel_dp.c | 66 +++++++++++++++++--
drivers/gpu/drm/i915/display/intel_dp.h | 9 +++
drivers/gpu/drm/i915/display/intel_dp_mst.c | 20 ++++--
drivers/gpu/drm/i915/i915_reg.h | 4 ++
6 files changed, 119 insertions(+), 23 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index 50a26bea8cde..385f9fcbdbed 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -3135,17 +3135,22 @@ static void intel_ddi_enable_fec(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state)
{
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+ enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
enum port port = encoder->port;
+ i915_reg_t ctl, status;
u32 val;
if (!crtc_state->fec_enable)
return;
- val = I915_READ(DP_TP_CTL(port));
+ ctl = intel_dp_tp_ctl_reg(dev_priv, cpu_transcoder, port);
+ status = intel_dp_tp_status_reg(dev_priv, cpu_transcoder, port);
+
+ val = I915_READ(ctl);
val |= DP_TP_CTL_FEC_ENABLE;
- I915_WRITE(DP_TP_CTL(port), val);
+ I915_WRITE(ctl, val);
- if (intel_de_wait_for_set(dev_priv, DP_TP_STATUS(port),
+ if (intel_de_wait_for_set(dev_priv, status,
DP_TP_STATUS_FEC_ENABLE_LIVE, 1))
DRM_ERROR("Timed out waiting for FEC Enable Status\n");
}
@@ -3154,16 +3159,19 @@ static void intel_ddi_disable_fec_state(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state)
{
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+ enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
enum port port = encoder->port;
+ i915_reg_t ctl;
u32 val;
if (!crtc_state->fec_enable)
return;
- val = I915_READ(DP_TP_CTL(port));
+ ctl = intel_dp_tp_ctl_reg(dev_priv, cpu_transcoder, port);
+ val = I915_READ(ctl);
val &= ~DP_TP_CTL_FEC_ENABLE;
- I915_WRITE(DP_TP_CTL(port), val);
- POSTING_READ(DP_TP_CTL(port));
+ I915_WRITE(ctl, val);
+ POSTING_READ(ctl);
}
static void intel_ddi_pre_enable_dp(struct intel_encoder *encoder,
@@ -3325,7 +3333,9 @@ static void intel_disable_ddi_buf(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state)
{
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+ enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
enum port port = encoder->port;
+ i915_reg_t ctl;
bool wait = false;
u32 val;
@@ -3336,10 +3346,11 @@ static void intel_disable_ddi_buf(struct intel_encoder *encoder,
wait = true;
}
- val = I915_READ(DP_TP_CTL(port));
+ ctl = intel_dp_tp_ctl_reg(dev_priv, cpu_transcoder, port);
+ val = I915_READ(ctl);
val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
val |= DP_TP_CTL_LINK_TRAIN_PAT1;
- I915_WRITE(DP_TP_CTL(port), val);
+ I915_WRITE(ctl, val);
/* Disable FEC in DP Sink */
intel_ddi_disable_fec_state(encoder, crtc_state);
@@ -3764,10 +3775,13 @@ static void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp)
struct drm_i915_private *dev_priv =
to_i915(intel_dig_port->base.base.dev);
enum port port = intel_dig_port->base.port;
+ i915_reg_t ctl;
u32 val;
bool wait = false;
+ enum transcoder cpu_transcoder = intel_dp_get_transcoder(intel_dp);
- if (I915_READ(DP_TP_CTL(port)) & DP_TP_CTL_ENABLE) {
+ ctl = intel_dp_tp_ctl_reg(dev_priv, cpu_transcoder, port);
+ if (I915_READ(ctl) & DP_TP_CTL_ENABLE) {
val = I915_READ(DDI_BUF_CTL(port));
if (val & DDI_BUF_CTL_ENABLE) {
val &= ~DDI_BUF_CTL_ENABLE;
@@ -3775,11 +3789,11 @@ static void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp)
wait = true;
}
- val = I915_READ(DP_TP_CTL(port));
+ val = I915_READ(ctl);
val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
val |= DP_TP_CTL_LINK_TRAIN_PAT1;
- I915_WRITE(DP_TP_CTL(port), val);
- POSTING_READ(DP_TP_CTL(port));
+ I915_WRITE(ctl, val);
+ POSTING_READ(ctl);
if (wait)
intel_wait_ddi_buf_idle(dev_priv, port);
@@ -3794,8 +3808,8 @@ static void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp)
if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
val |= DP_TP_CTL_ENHANCED_FRAME_ENABLE;
}
- I915_WRITE(DP_TP_CTL(port), val);
- POSTING_READ(DP_TP_CTL(port));
+ I915_WRITE(ctl, val);
+ POSTING_READ(ctl);
intel_dp->DP |= DDI_BUF_CTL_ENABLE;
I915_WRITE(DDI_BUF_CTL(port), intel_dp->DP);
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index b7da955954b7..6334c313f92e 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1214,6 +1214,7 @@ struct intel_dp {
bool can_mst; /* this port supports mst */
bool is_mst;
int active_mst_links;
+ enum transcoder mst_master_trans; /* Only valid on TGL+ */
/* connector directly attached - won't be use for modeset in mst world */
struct intel_connector *attached_connector;
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 5c45a3bb102d..372719c90c14 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -3205,6 +3205,51 @@ static void chv_post_disable_dp(struct intel_encoder *encoder,
vlv_dpio_put(dev_priv);
}
+i915_reg_t intel_dp_tp_ctl_reg(const struct drm_i915_private *dev_priv,
+ enum transcoder cpu_transcoder,
+ enum port port)
+{
+ if (INTEL_GEN(dev_priv) >= 12) {
+ WARN_ON(cpu_transcoder == TRANSCODER_INVALID);
+ return TGL_DP_TP_CTL(cpu_transcoder);
+ } else {
+ return DP_TP_CTL(port);
+ }
+}
+
+i915_reg_t intel_dp_tp_status_reg(const struct drm_i915_private *dev_priv,
+ enum transcoder cpu_transcoder,
+ enum port port)
+{
+ if (INTEL_GEN(dev_priv) >= 12) {
+ WARN_ON(cpu_transcoder == TRANSCODER_INVALID);
+ return TGL_DP_TP_STATUS(cpu_transcoder);
+ } else {
+ return DP_TP_STATUS(port);
+ }
+}
+
+/*
+ * Return the transcoder that this intel_dp port is driven.
+ * When in MST mode it will return the master transcoder of the MST so do not
+ * use it when reading or writing registers in the slave transcoders.
+ */
+enum transcoder intel_dp_get_transcoder(struct intel_dp *intel_dp)
+{
+ struct intel_connector *connector;
+ struct drm_connector_state *conn_state;
+ struct intel_crtc_state *crtc_state;
+
+ if (intel_dp->is_mst)
+ return intel_dp->mst_master_trans;
+
+ connector = intel_dp->attached_connector;
+ conn_state = connector->base.state;
+ crtc_state = to_intel_crtc_state(conn_state->crtc->state);
+
+ return crtc_state->cpu_transcoder;
+}
+
static void
_intel_dp_set_link_train(struct intel_dp *intel_dp,
u32 *DP,
@@ -3220,8 +3265,13 @@ _intel_dp_set_link_train(struct intel_dp *intel_dp,
dp_train_pat & train_pat_mask);
if (HAS_DDI(dev_priv)) {
- u32 temp = I915_READ(DP_TP_CTL(port));
+ enum transcoder cpu_transcoder;
+ i915_reg_t ctl;
+ u32 temp;
+ cpu_transcoder = intel_dp_get_transcoder(intel_dp);
+ ctl = intel_dp_tp_ctl_reg(dev_priv, cpu_transcoder, port);
+ temp = I915_READ(ctl);
if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE)
temp |= DP_TP_CTL_SCRAMBLE_DISABLE;
else
@@ -3246,7 +3296,7 @@ _intel_dp_set_link_train(struct intel_dp *intel_dp,
temp |= DP_TP_CTL_LINK_TRAIN_PAT4;
break;
}
- I915_WRITE(DP_TP_CTL(port), temp);
+ I915_WRITE(ctl, temp);
} else if ((IS_IVYBRIDGE(dev_priv) && port == PORT_A) ||
(HAS_PCH_CPT(dev_priv) && port != PORT_A)) {
@@ -3939,15 +3989,21 @@ void intel_dp_set_idle_link_train(struct intel_dp *intel_dp)
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
enum port port = intel_dig_port->base.port;
+ enum transcoder cpu_transcoder;
+ i915_reg_t ctl, status;
u32 val;
if (!HAS_DDI(dev_priv))
return;
- val = I915_READ(DP_TP_CTL(port));
+ cpu_transcoder = intel_dp_get_transcoder(intel_dp);
+ ctl = intel_dp_tp_ctl_reg(dev_priv, cpu_transcoder, port);
+ status = intel_dp_tp_status_reg(dev_priv, cpu_transcoder, port);
+
+ val = I915_READ(ctl);
val &= ~DP_TP_CTL_LINK_TRAIN_MASK;
val |= DP_TP_CTL_LINK_TRAIN_IDLE;
- I915_WRITE(DP_TP_CTL(port), val);
+ I915_WRITE(ctl, val);
/*
* On PORT_A we can have only eDP in SST mode. There the only reason
@@ -3959,7 +4015,7 @@ void intel_dp_set_idle_link_train(struct intel_dp *intel_dp)
if (port == PORT_A)
return;
- if (intel_de_wait_for_set(dev_priv, DP_TP_STATUS(port),
+ if (intel_de_wait_for_set(dev_priv, status,
DP_TP_STATUS_IDLE_DONE, 1))
DRM_ERROR("Timed out waiting for DP idle patterns\n");
}
diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h
index 657bbb1f5ed0..107129b5d9a3 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.h
+++ b/drivers/gpu/drm/i915/display/intel_dp.h
@@ -11,6 +11,7 @@
#include <drm/i915_drm.h>
#include "i915_reg.h"
+#include "intel_display.h"
enum pipe;
struct drm_connector_state;
@@ -113,6 +114,14 @@ int intel_dp_link_required(int pixel_clock, int bpp);
int intel_dp_max_data_rate(int max_link_clock, int max_lanes);
bool intel_digital_port_connected(struct intel_encoder *encoder);
+i915_reg_t intel_dp_tp_ctl_reg(const struct drm_i915_private *dev_priv,
+ enum transcoder cpu_transcoder,
+ enum port port);
+i915_reg_t intel_dp_tp_status_reg(const struct drm_i915_private *dev_priv,
+ enum transcoder cpu_transcoder,
+ enum port port);
+enum transcoder intel_dp_get_transcoder(struct intel_dp *intel_dp);
+
static inline unsigned int intel_dp_unused_lane_mask(int lane_count)
{
return ~((1 << lane_count) - 1) & 0xf;
diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
index 670a12fd2f27..057582f0b5d5 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
@@ -354,9 +354,11 @@ static void intel_mst_pre_pll_enable_dp(struct intel_encoder *encoder,
struct intel_digital_port *intel_dig_port = intel_mst->primary;
struct intel_dp *intel_dp = &intel_dig_port->dp;
- if (intel_dp->active_mst_links == 0)
+ if (intel_dp->active_mst_links == 0) {
+ intel_dp->mst_master_trans = pipe_config->mst_master_trans;
intel_dig_port->base.pre_pll_enable(&intel_dig_port->base,
pipe_config, NULL);
+ }
}
static void intel_mst_post_pll_disable_dp(struct intel_encoder *encoder,
@@ -384,6 +386,7 @@ static void intel_mst_pre_enable_dp(struct intel_encoder *encoder,
enum port port = intel_dig_port->base.port;
struct intel_connector *connector =
to_intel_connector(conn_state->connector);
+ i915_reg_t status;
int ret;
u32 temp;
@@ -412,8 +415,12 @@ static void intel_mst_pre_enable_dp(struct intel_encoder *encoder,
DRM_ERROR("failed to allocate vcpi\n");
intel_dp->active_mst_links++;
- temp = I915_READ(DP_TP_STATUS(port));
- I915_WRITE(DP_TP_STATUS(port), temp);
+
+ status = intel_dp_tp_status_reg(dev_priv,
+ pipe_config->mst_master_trans,
+ port);
+ temp = I915_READ(status);
+ I915_WRITE(status, temp);
ret = drm_dp_update_payload_part1(&intel_dp->mst_mgr);
@@ -429,10 +436,15 @@ static void intel_mst_enable_dp(struct intel_encoder *encoder,
struct intel_dp *intel_dp = &intel_dig_port->dp;
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
enum port port = intel_dig_port->base.port;
+ i915_reg_t status;
DRM_DEBUG_KMS("active links %d\n", intel_dp->active_mst_links);
- if (intel_de_wait_for_set(dev_priv, DP_TP_STATUS(port),
+ status = intel_dp_tp_status_reg(dev_priv,
+ pipe_config->mst_master_trans,
+ port);
+
+ if (intel_de_wait_for_set(dev_priv, status,
DP_TP_STATUS_ACT_SENT, 1))
DRM_ERROR("Timed out waiting for ACT sent\n");
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index c1b779c40fa8..c28f6ff5e594 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -9453,7 +9453,9 @@ enum skl_power_gate {
/* DisplayPort Transport Control */
#define _DP_TP_CTL_A 0x64040
#define _DP_TP_CTL_B 0x64140
+#define _TGL_DP_TP_CTL_A 0x60540
#define DP_TP_CTL(port) _MMIO_PORT(port, _DP_TP_CTL_A, _DP_TP_CTL_B)
+#define TGL_DP_TP_CTL(tran) _MMIO_TRANS2((tran), _TGL_DP_TP_CTL_A)
#define DP_TP_CTL_ENABLE (1 << 31)
#define DP_TP_CTL_FEC_ENABLE (1 << 30)
#define DP_TP_CTL_MODE_SST (0 << 27)
@@ -9473,7 +9475,9 @@ enum skl_power_gate {
/* DisplayPort Transport Status */
#define _DP_TP_STATUS_A 0x64044
#define _DP_TP_STATUS_B 0x64144
+#define _TGL_DP_TP_STATUS_A 0x60544
#define DP_TP_STATUS(port) _MMIO_PORT(port, _DP_TP_STATUS_A, _DP_TP_STATUS_B)
+#define TGL_DP_TP_STATUS(tran) _MMIO_TRANS2((tran), _TGL_DP_TP_STATUS_A)
#define DP_TP_STATUS_FEC_ENABLE_LIVE (1 << 28)
#define DP_TP_STATUS_IDLE_DONE (1 << 25)
#define DP_TP_STATUS_ACT_SENT (1 << 24)
--
2.21.0
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next prev parent reply other threads:[~2019-08-17 9:39 UTC|newest]
Thread overview: 90+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-08-17 9:38 [PATCH v2 00/40] Tiger Lake batch 3 Lucas De Marchi
2019-08-17 9:38 ` [PATCH v2 01/40] drm/i915/tgl: disable DDIC Lucas De Marchi
2019-08-19 17:16 ` Matt Roper
2019-08-17 9:38 ` [PATCH v2 02/40] drm/i915/tgl: add support for reading the timestamp frequency Lucas De Marchi
2019-08-17 9:38 ` [PATCH v2 03/40] drm/i915/tgl: Move transcoders to pipes' powerwells Lucas De Marchi
2019-08-19 11:59 ` Imre Deak
2019-08-17 9:38 ` [PATCH v2 04/40] drm/i915/tgl: update DMC firmware to 2.04 Lucas De Marchi
2019-08-19 17:55 ` Srivatsa, Anusha
2019-08-19 18:03 ` Lucas De Marchi
2019-08-19 18:07 ` Srivatsa, Anusha
2019-08-17 9:38 ` [PATCH v2 05/40] drm/i915/psr: Make PSR registers relative to transcoders Lucas De Marchi
2019-08-20 20:16 ` Lucas De Marchi
2019-08-20 21:15 ` Souza, Jose
2019-08-17 9:38 ` [PATCH v2 06/40] drm/i915: Add transcoder restriction to PSR2 Lucas De Marchi
2019-08-20 20:19 ` Lucas De Marchi
2019-08-21 14:50 ` Ville Syrjälä
2019-08-17 9:38 ` [PATCH v2 07/40] drm/i915: Do not unmask PSR interruption in IRQ postinstall Lucas De Marchi
2019-08-20 20:29 ` Lucas De Marchi
2019-08-20 22:20 ` Souza, Jose
2019-08-17 9:38 ` [PATCH v2 08/40] drm/i915/psr: Only handle interruptions of the transcoder in use Lucas De Marchi
2019-08-17 9:38 ` [PATCH v2 09/40] drm/i915/bdw+: Enable PSR in any eDP port Lucas De Marchi
2019-08-17 9:38 ` [PATCH v2 10/40] drm/i915: Guard and warn if more than one eDP panel is present Lucas De Marchi
2019-08-17 9:38 ` [PATCH v2 11/40] drm/i915: Do not read PSR2 register in transcoders without PSR2 Lucas De Marchi
2019-08-17 9:38 ` [PATCH v2 12/40] drm/i915/tgl: PSR link standby is not supported anymore Lucas De Marchi
2019-08-17 9:38 ` [PATCH v2 13/40] drm/i915/tgl: Access the right register when handling PSR interruptions Lucas De Marchi
2019-08-17 9:38 ` [PATCH v2 14/40] drm/i915/tgl: Add maximum resolution supported by PSR2 HW Lucas De Marchi
2019-08-17 9:38 ` [PATCH v2 15/40] drm/i915: Fix DP-MST crtc_mask Lucas De Marchi
2019-08-17 9:38 ` [PATCH v2 16/40] drm/i915: Add for_each_new_intel_connector_in_state() Lucas De Marchi
2019-08-21 13:13 ` Kahola, Mika
2019-08-17 9:38 ` [PATCH v2 17/40] drm: Add for_each_oldnew_intel_crtc_in_state_reverse() Lucas De Marchi
2019-08-21 11:22 ` Kahola, Mika
2019-08-21 13:32 ` Kahola, Mika
2019-08-17 9:38 ` [PATCH v2 18/40] drm/i915: Disable pipes in reverse order Lucas De Marchi
2019-08-21 11:29 ` Kahola, Mika
2019-08-17 9:38 ` [PATCH v2 19/40] drm/i915/tgl: Select master transcoder in DP MST Lucas De Marchi
2019-08-22 12:43 ` Jani Nikula
2019-08-22 16:44 ` Maarten Lankhorst
2019-08-17 9:38 ` [PATCH v2 20/40] drm/i915/tgl: Introduce initial Tiger Lake workarounds Lucas De Marchi
2019-08-17 9:38 ` [PATCH v2 21/40] drm/i915/tgl: Enable VD HCP/MFX sub-pipe power gating Lucas De Marchi
2019-08-20 20:54 ` Lucas De Marchi
2019-08-21 9:16 ` Ye, Tony
2019-08-17 9:38 ` [PATCH v2 22/40] drm/i915/tgl: Do not apply WaIncreaseDefaultTLBEntries from GEN12 onwards Lucas De Marchi
2019-08-20 23:29 ` Summers, Stuart
2019-08-22 0:25 ` Summers, Stuart
2019-08-17 9:38 ` [PATCH v2 23/40] drm/i915/tgl: Register state context definition for Gen12 Lucas De Marchi
2019-08-21 21:12 ` Daniele Ceraolo Spurio
2019-08-22 13:31 ` Mika Kuoppala
2019-08-22 14:51 ` Chris Wilson
2019-08-17 9:38 ` Lucas De Marchi [this message]
2019-08-17 9:38 ` [PATCH v2 25/40] drm/i915/tgl: Implement TGL DisplayPort training sequence Lucas De Marchi
2019-08-20 22:01 ` [PATCH v2] " José Roberto de Souza
2019-08-20 23:07 ` Manasi Navare
2019-08-21 20:22 ` Souza, Jose
[not found] ` <20190821213233.1067-1-jose.souza@intel.com>
2019-08-22 11:00 ` [PATCH v3] " Maarten Lankhorst
2019-08-17 9:38 ` [PATCH v2 26/40] HACK: drm/i915/tgl: Gen12 render context size Lucas De Marchi
2019-08-20 10:36 ` Chris Wilson
2019-08-22 13:42 ` Mika Kuoppala
2019-08-22 13:48 ` Chris Wilson
2019-08-17 9:38 ` [PATCH v2 27/40] drm/i915/tgl: add Gen12 default indirect ctx offset Lucas De Marchi
2019-08-17 9:38 ` [PATCH v2 28/40] drm/i915/tgl: add GEN12_MAX_CONTEXT_HW_ID Lucas De Marchi
2019-08-21 14:43 ` Lisovskiy, Stanislav
2019-08-17 9:38 ` [PATCH v2 29/40] drm/i915/tgl: Gen12 csb support Lucas De Marchi
2019-08-17 9:38 ` [PATCH v2 30/40] drm/i915/tgl: Report valid VDBoxes with SFC capability Lucas De Marchi
2019-08-17 9:38 ` [PATCH v2 31/40] rm/i915/tgl: Move GTCR register to cope with GAM MMIO address remap Lucas De Marchi
2019-08-20 20:43 ` Lucas De Marchi
2019-08-22 13:28 ` Mika Kuoppala
2019-08-23 0:44 ` Lucas De Marchi
2019-08-17 9:38 ` [PATCH v2 32/40] drm/i915/tgl: Updated Private PAT programming Lucas De Marchi
2019-08-20 10:33 ` Chris Wilson
2019-08-17 9:38 ` [PATCH v2 33/40] drm/i915/tgl/perf: use the same oa ctx_id format as icl Lucas De Marchi
2019-08-21 12:36 ` Lionel Landwerlin
2019-08-17 9:38 ` [PATCH v2 34/40] drm/i915/perf: add a parameter to control the size of OA buffer Lucas De Marchi
2019-08-17 9:38 ` [PATCH v2 35/40] drm/i915/tgl: Add perf support on TGL Lucas De Marchi
2019-08-17 9:38 ` [PATCH v2 36/40] drm/i915/tgl: Gen-12 display loses Yf tiling and legacy CCS support Lucas De Marchi
2019-08-17 9:38 ` [PATCH v2 37/40] drm/framebuffer/tgl: Format modifier for Intel Gen-12 render compression Lucas De Marchi
2019-08-21 14:34 ` Lisovskiy, Stanislav
2019-08-17 9:39 ` [PATCH v2 38/40] drm/i915/tgl: Gen-12 render decompression Lucas De Marchi
2019-08-17 9:39 ` [PATCH v2 39/40] drm/framebuffer/tgl: Format modifier for Intel Gen-12 media compression Lucas De Marchi
2019-08-21 14:40 ` Lisovskiy, Stanislav
2019-08-17 9:39 ` [PATCH v2 40/40] drm/i915/tgl: " Lucas De Marchi
2019-08-21 14:36 ` Lisovskiy, Stanislav
2019-08-17 9:49 ` ✗ Fi.CI.CHECKPATCH: warning for Tiger Lake batch 3 (rev2) Patchwork
2019-08-17 10:03 ` ✗ Fi.CI.SPARSE: " Patchwork
2019-08-17 10:12 ` ✗ Fi.CI.BAT: failure " Patchwork
2019-08-20 10:28 ` ✗ Fi.CI.CHECKPATCH: warning for Tiger Lake batch 3 (rev3) Patchwork
2019-08-20 10:42 ` ✗ Fi.CI.SPARSE: " Patchwork
2019-08-20 12:15 ` ✗ Fi.CI.BAT: failure " Patchwork
2019-08-20 12:36 ` ✓ Fi.CI.BAT: success " Patchwork
2019-08-20 17:59 ` ✓ Fi.CI.IGT: " Patchwork
2019-08-20 22:30 ` ✗ Fi.CI.BAT: failure for Tiger Lake batch 3 (rev4) Patchwork
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